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ryu: configure plld for display usage

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The kernel doesn't have the logic for bringing up the plld.
Therefore, configure it in the firmware. The clock used
is an interim value until the display controller sequencing
is fully implemented.

BUG=chrome-os-partner:31640
BRANCH=None
TEST=Noted configured freq is close to requested. Also, no
     more plld errors observed from the kernel.

Change-Id: I6f57d5c48630385d1814e7ef61898a2d49c8f747
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214841
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Aaron Durbin 2014-08-28 15:49:31 -05:00 • committed by chrome-internal-fetch
commit b44956ec87
1 changed files with 9 additions and 0 deletions
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9
src/mainboard/google/rush_ryu/mainboard.c
View file

@ -50,7 +50,16 @@ static const struct funit_cfg funits[] = {
static void mainboard_init(device_t dev)
{
/* PLLD should be 2 * pixel clock (301620khz). */
const uint32_t req_disp_clk = 301620 * 1000 * 2;
uint32_t disp_clk;
soc_configure_funits(funits, ARRAY_SIZE(funits));
disp_clk = clock_display(req_disp_clk);
if (disp_clk != req_disp_clk)
printk(BIOS_DEBUG, "display clock: %u vs %u (r)\n", disp_clk,
req_disp_clk);
}
static void mainboard_enable(device_t dev)