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samus: Move PEI data structure init to separate file

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This needs to be executed in both romstage and ramstage
for the different PEI binary stages.

It uses the broadwell interface now instead of haswell.

BUG=chrome-os-partner:28234
TEST=Build and boot on samus
CQ-DEPEND=CL:199920
CQ-DEPEND=CL:199922
CQ-DEPEND=CL:199923
CQ-DEPEND=CL:199943
CQ-DEPEND=CL:*163751

Change-Id: Ida05bd17b9e54f08ed0e2767361c9301a2e97709
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199921
This commit is contained in:
Duncan Laurie 2014-05-14 16:01:08 -07:00 • committed by chrome-internal-fetch
commit 89f98a27ea
3 changed files with 88 additions and 54 deletions
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3
src/mainboard/google/samus/Makefile.inc
View file

@ -24,6 +24,9 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
romstage-y += pei_data.c
ramstage-y += pei_data.c
## DIMM SPD for on-board memory
romstage-y += spd.c
SPD_BIN = $(obj)/spd.bin

81
src/mainboard/google/samus/pei_data.c Normal file
View file

@ -0,0 +1,81 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdint.h>
#include <string.h>
#include <broadwell/gpio.h>
#include <broadwell/pei_data.h>
#include <broadwell/pei_wrapper.h>
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
/* DQ byte map for Samus board */
const u8 dq_map[2][6][2] = {
{ { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
{ 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } },
{ { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
{ 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } } };
/* DQS CPU<>DRAM map for Samus board */
const u8 dqs_map[2][8] = {
{ 2, 0, 1, 3, 6, 4, 7, 5 },
{ 2, 1, 0, 3, 6, 5, 4, 7 } };
pei_data->ec_present = 1;
/* One installed DIMM per channel */
pei_data->dimm_channel0_disabled = 2;
pei_data->dimm_channel1_disabled = 2;
memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
/* P0: HOST PORT */
pei_data_usb2_port(pei_data, 0, 0x0080, 1, 0,
USB_PORT_BACK_PANEL);
/* P1: HOST PORT */
pei_data_usb2_port(pei_data, 1, 0x0080, 1, 1,
USB_PORT_BACK_PANEL);
/* P2: EMPTY */
pei_data_usb2_port(pei_data, 2, 0x0000, 0, USB_OC_PIN_SKIP,
USB_PORT_SKIP);
/* P3: SD CARD */
pei_data_usb2_port(pei_data, 3, 0x0040, 0, USB_OC_PIN_SKIP,
USB_PORT_INTERNAL);
/* P4: EMPTY */
pei_data_usb2_port(pei_data, 4, 0x0000, 0, USB_OC_PIN_SKIP,
USB_PORT_SKIP);
/* P5: WWAN */
pei_data_usb2_port(pei_data, 5, 0x0040, 1, USB_OC_PIN_SKIP,
USB_PORT_INTERNAL);
/* P6: CAMERA */
pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP,
USB_PORT_INTERNAL);
/* P7: BT */
pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP,
USB_PORT_INTERNAL);
/* P1: HOST PORT */
pei_data_usb3_port(pei_data, 0, 1, 0, 0);
/* P2: HOST PORT */
pei_data_usb3_port(pei_data, 1, 1, 1, 0);
/* P3: EMPTY */
pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0);
/* P4: SD CARD */
pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0);
}

58
src/mainboard/google/samus/romstage.c
View file

@ -72,60 +72,7 @@ const struct rcba_config_instruction rcba_config[] = {
void mainboard_romstage_entry(unsigned long bist)
{
struct pei_data pei_data = {
pei_version: PEI_VERSION,
mchbar: DEFAULT_MCHBAR,
dmibar: DEFAULT_DMIBAR,
epbar: DEFAULT_EPBAR,
pciexbar: DEFAULT_PCIEXBAR,
smbusbar: SMBUS_IO_BASE,
wdbbar: 0x4000000,
wdbsize: 0x1000,
hpet_address: HPET_ADDR,
rcba: DEFAULT_RCBA,
pmbase: DEFAULT_PMBASE,
gpiobase: DEFAULT_GPIOBASE,
temp_mmio_base: 0xfed08000,
system_type: 5, /* ULT */
tseg_size: CONFIG_SMM_TSEG_SIZE,
spd_addresses: { 0xff, 0x00, 0xff, 0x00 },
ec_present: 1,
// 0 = leave channel enabled
// 1 = disable dimm 0 on channel
// 2 = disable dimm 1 on channel
// 3 = disable dimm 0+1 on channel
dimm_channel0_disabled: 2,
dimm_channel1_disabled: 2,
max_ddr3_freq: 1600,
usb_xhci_on_resume: 1,
usb2_ports: {
/* Length, Enable, OCn#, Location */
{ 0x0080, 1, 0, /* P0: HOST PORT */
USB_PORT_BACK_PANEL },
{ 0x0080, 1, 1, /* P1: HOST PORT */
USB_PORT_BACK_PANEL },
{ 0x0000, 0, USB_OC_PIN_SKIP, /* P2: EMPTY */
USB_PORT_SKIP },
{ 0x0040, 1, USB_OC_PIN_SKIP, /* P3: SD CARD */
USB_PORT_INTERNAL },
{ 0x0000, 0, USB_OC_PIN_SKIP, /* P4: EMPTY */
USB_PORT_SKIP },
{ 0x0040, 1, USB_OC_PIN_SKIP, /* P5: WWAN */
USB_PORT_INTERNAL },
{ 0x0040, 1, USB_OC_PIN_SKIP, /* P6: CAMERA */
USB_PORT_INTERNAL },
{ 0x0040, 1, USB_OC_PIN_SKIP, /* P7: BT */
USB_PORT_INTERNAL },
},
usb3_ports: {
/* Enable, OCn# */
{ 1, 0 }, /* P1: HOST PORT */
{ 1, 1 }, /* P2: HOST PORT */
{ 0, USB_OC_PIN_SKIP }, /* P3: EMPTY */
{ 1, USB_OC_PIN_SKIP }, /* P4: SD CARD */
},
};
struct pei_data pei_data;
struct romstage_params romstage_params = {
.pei_data = &pei_data,
.gpio_map = &mainboard_gpio_map,
@ -133,6 +80,9 @@ void mainboard_romstage_entry(unsigned long bist)
.bist = bist,
};
/* Fill out PEI DATA */
memset(&pei_data, 0, sizeof(pei_data));
mainboard_fill_pei_data(&pei_data);
mainboard_fill_spd_data(&pei_data);
/* Call into the real romstage main with this board's attributes. */