Reserve a small persistent SMRAM subregion for OPAL S3 unlock state, so
the payload-provided OPAL secret can survive SMM handler reload on S3
resume.
Expose the region base/size to SMM via smm_runtime and provide an
accessor for SMM code. Clear the region on cold boot/reboot, but
preserve it when waking from S3.
TEST=tested with rest of patch train
Change-Id: Ib1e92edb31c845367afe6185e5fa18ab1bc71108
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Intel Document 492662 (Haswell System Agent BIOS Spec), Rev 1.6.0 states
that `ARCHDIS` (VT engine BAR, offset 0xff0) has to be written fully, as
well as several other things that were not done properly in coreboot. As
these steps are Haswell-specific, introduce two helper functions to test
if the CPU is Haswell or Broadwell.
Intel Document 535094 (Broadwell BIOS Spec), Rev 2.2.0 contains the same
steps for Broadwell. To permit unifying Haswell and Broadwell, implement
the Broadwell steps as well.
Change-Id: I077e064754720d9f9f627733c954712a2b24b5b7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91631
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Update the entries for Crystalwell and Broadwell ULT, and add the CPUIDs
for Crystalwell B0 and Broadwell G0. Also drop a now-done FIXME comment.
Change-Id: Ib5293b5a0ef3321678c68363fb4bc8999b10cd01
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91626
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 8b0636e06f ("cpu/intel/haswell: Clean up CPUID definitions")
used the wrong value for the `CRYSTALWELL_FAMILY` macro. Also, as per
Intel document 634961-024 (Broadwell-H Specification Update), the one
production Broadwell Trad stepping is G0, not C0. And for the sake of
completeness, add the `BROADWELL_FAMILY_TRAD` macro.
Tested with BUILD_TIMELESS=1, Purism Librem 15 v2 remains identical.
Change-Id: I25be5289997000e116cc36cf427a9d4970a3ec1b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91625
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This function prints CPU information, so it makes sense for it to be
part of CPU code. Subsequent commits will update the CPUID table and
make the Haswell northbridge code also use it.
For now, rename the static function in `nb/intel/haswell` to avoid a
name clash. It will be dropped in a follow-up anyway.
Change-Id: I6b26fddd4e899b692f4122921db1c70f4b16b4f2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91624
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Provide an optional, coreboot-managed CBMEM scratch buffer for SMM code.
CBMEM is reserved from the OS via the memory map and persists across S3,
so it is suitable for firmware-owned DMA buffers used during resume.
SMRAM is not device DMA-accessible, so this scratch buffer must live
outside SMRAM.
Pass the base/size to SMM via smm_runtime so SMM code can validate
placement and avoid relying on untrusted pointers.
The CBMEM region size is configurable via SMM_OPAL_S3_SCRATCH_SIZE,
defaulting to 16 KiB as a safe value.
TEST=tested with rest of patch train
Change-Id: I79ae5327f27e574b151b7cf456761fa0d7038f2f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Commit 4c4bd3cd97 ("soc/intel/broadwell: Hook up PCI domain and CPU
cluster ops to devicetree") and commit 600fa266bd ("nb/intel/haswell:
Hook up PCI domain and CPU cluster ops to devicetree") decoupled the CPU
bus device operations from northbridge code. Since Haswell and Broadwell
both use the same CPU code, move the CPU bus ops to CPU code in order to
deduplicate them.
Change-Id: I11cbff3d87e233f40a40f2fc70840f6bf35b0cb9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91463
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Extend get_microcode_info() to return the microcode size.
This is being used in the following commit which uses the size
to copy the microcode update to RAM in order to speed up MPinit.
Depending on the SPI flash interface speed, the microcode size and
the number of APs this can improve boot time by seconds.
Since microcode size isn't used yet this is not a functional change.
Change-Id: I1385e04c56e1411f0847a1c201c17e460c957477
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90894
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use existing define for SMRR and PMRR support instead of redefining
it in various places.
TEST=No functional change, thus untested.
Change-Id: Ie366a9d695800acd9713bd4e8393201a1f0a5ab2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91015
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For most targets it's known if the CPU supports alternative SMRR
registers or not. Only on model_6fx runtime detection is necessary.
On all platforms this allows the compiler to optimize the code and
thus shrink the code size if alternative SMRR aren't supported.
TEST=On Lenovo X220 the ramstage is 308 bytes smaller.
Change-Id: I3a965d142f79ad587b8cedc9b4646b05e2a45f8b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91014
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Ensure that BSP has latest microcode loaded before MPinit starts.
This aligns the code with other platforms ensuring that the microcode
on the BSP is up to date.
It likely has updated microcode before enabling NEM, so this is a
nop, but it also ensures that the microcode is located in CBFS
before the MTRRs are setup using x86_setup_mtrrs_with_detect() which
removes caching the SPI flash MMIO area.
Since intel_microcode_find() caches the microcode location
get_microcode_info() will be faster since it doesn't need to access
the CBFS.
TEST=Lenovo X220 still boots.
Change-Id: Ic4c5d1a06ce314b38b92e8a9c089ed901716ff27
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90893
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Ancient microcode update files do not have a total_size field.
Add support for such platforms and return 2048 in that case.
Change-Id: I952edc12cccf24f396d940bc594d8ef97826a253
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90910
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
On Arrow Lake we ran out of variable MTRRs, leaving PCI BARs uncached.
This made the edk2 setup UI extremely slow due to UC MMIO/framebuffer
writes.
Ensure BAR ranges get a cacheable attribute instead of falling back to
UC.
Change-Id: I74a89cf334d1eb74bbfbb4b0f9621f098bfa4a89
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91109
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The code was copied from newer generation SoC supporting parallel
SMM relocation, but it wasn't properly cleaned.
Gen1 doesn't support parallel SMM relocation, so fix the comments.
Change-Id: Idbe6d2c18f668a9c1922b93ce1b2cc3d126ff2f9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91013
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce platform_romstage_pre_mem() and platform_romstage_post_mem()
as weak symbols in the x86 romstage cycle.
These hooks allow SoCs and mainboards to execute low-level setup or
instrumentation immediately before and after memory initialization
without modifying the core romstage.c flow.
- platform_romstage_pre_mem: Called before mainboard_romstage_entry.
- platform_romstage_post_mem: Called after memory is up but while still
running on the Cache-as-RAM (CAR) stack.
Change-Id: I59cb115de0d512106d9a029d683c10b025076893
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90999
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The generic Intel SMM S5 entry path disables all GPEs before asserting
SLP_EN, which clears OS-armed wake enables (e.g. LAN_WAKE) and prevents
Wake-on-LAN from S5.
Add a mainboard override hook, mainboard_smi_sleep_finalize(), called
after the S5 teardown but before SLP_EN is asserted, allowing boards to
restore required wake sources.
Change-Id: I9e97308ed94961fc4c08a10714b1b53f198bb593
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Take advantage of cbfstool's ability to operate on multiple regions and
introduce a variable with a list of main CBFS regions: it's just
"COREBOOT" in most cases, but becomes "COREBOOT,COREBOOT_TS" when Top
Swap update mechanism is enabled (see [0]).
This is meant to simplify Makefiles by avoiding extra branches in
existing and future changes.
[0]: https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/
Change-Id: If537d0d21a2867fafc2241ea9a0b4c0c6ca290a8
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90435
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-by: Filip Gołaś <filip.golas@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
This is a correction of CB:89570 (commit 04ea4724e2 ("Makefile.mk:
separate bootblocks into BOOTBLOCK and TOPSWAP")) which has FITs in both
BOOTBLOCK and TOPSWAP point at microcode in COREBOOT region.
This can be tested by comparing outputs of
build/util/cbfstool/ifittool -f build/coreboot.rom -r TOPSWAP -D
and
build/util/cbfstool/ifittool -f build/coreboot.rom -r BOOTBLOCK -D
with microcode addresses as shown by
uefitool build/coreboot.rom
The addresses in two regions must not be identical and their last six
hex digits must match what uefitool shows in "Base:" field (not
"Offset:").
Change-Id: Ie37aee7a26be18d1a4d8993afd2a2484c38c0b1e
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Filip Gołaś <filip.golas@3mdeb.com>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
AMD systems have a TOM2WB bit in SYS_CFG MSR to forcefully cover the
address space between 4GB-TOM2 as WB. Any WB MTRR that falls into that
range may be skipped from programming. It can save a lot of MTRRs when
calculating the MTRR solution. It is especially needed when using a
temporary MTRR to cover the flash as WP, as the MTRR space gets more
fragmented.
Add checks for SYS_CFG TOM2WB in the MTRR driver and skip the WB MTRR
ranges when possible.
TEST=Successfully enable temporary MTRR range for flash on Gigabyte
MZ33-AR1.
Change-Id: Ie9af9b54a1037c843d8f019506af761a8d8769d0
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89199
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MP Specification v1.4 says to program the spurious interrupt
in the following way:
"The APIC spurious interrupt must point to a vector whose lower
nibble is 0F, that is 0xF, where x is 0 - F. Here we use Int 00FH,
which handles spurious interrupts and supplies the necessary IRET.
This vector is assumed to have already been initialized in memory."
Follow the requirement and set the spurious interrupt vector
to 0x0F. This is what reference implementations, like EDK2, and also
BIOS vendors do.
Change-Id: I7bde413bbadca1de0079daf52b5501ba6638a4c3
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The option was introduced by
commit ae738acdc5 ("cpu/x86: Support CPUs without rdmsr/wrmsr")
for the intel quark SOC. However the SOC doesn't exist anymore in
coreboot. Nor does any other SOC use this option.
Therefore remove it.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I4f3f5e91c00784c159042271387c2e862f351881
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90421
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If the Top Swap mechanism is enabled, after running the bootblock from
the TOP_SWAP region, boot from an updatable COREBOOT_TS FMAP region.
Having flashed the TOP_SWAP bootblock and COREBOOT_TS, this allows the
user to boot a newer version of the firmware with the ability to
revert to the previous known-good version by performing a CMOS reset.
Requires having a read-write COREBOOT_TS region in the FMAP file.
This is part of an ongoing implementation of a redundancy feature
proposed on the mailing list:
https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/
TEST=Boot Protectli VP6650, setting the attempt_slot_b flag to
different values, observing the "Booting from COREBOOT/COREBOOT_TS
region" prints correspondingly.
Change-Id: Ieadc9bfbe940cbec79eb84f16a5d622bfbb82ede
Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Add Kconfig INTEL_TOP_SWAP_SEPARATE_REGIONS. When enabled, place the
regular bootblock in BOOTBLOCK and the Top Swap bootblock in TOPSWAP
to simplify A B updates. This lays groundwork for redundancy where one
bootblock remains a read only golden copy and the other is replaceable.
No swap control logic is added in this change. The option depends on
INTEL_ADD_TOP_SWAP_BOOTBLOCK and defaults to n so existing builds are
unchanged. A custom .fmd is required with BOOTBLOCK and TOPSWAP added
at the end of the image.
Background and update flow are described here:
Link: https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5Y
V35/
TEST=Build and run Protectli VP6650 (ADL-P), boots successfully with
correct microcode
Change-Id: I489406dd8d08ad85bb46324d3d009acb49b6c52a
Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
This commit makes the tile and die ID CPU topology parameters
information available to support the implementation of
EFI_MP_SERVICES_PROTOCOL.GetProcessorInfo() in accordance with the
Platform Initialization Specification 1.7.
TEST=Instrumentation shows that the tile_id and die_id apic_path fields
are properly populated.
Change-Id: If4d473901c8de02b3d6cef44f5481a1864f14d64
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89461
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On older CPUs lacking ESRM (Enhanced Short Rep Mov) the rep stos
instructions are very slow. Since the MTRR that covers the SPI ROM
is disabled when setting up the NEM, the CPU will run with cache
disabled and is even slower.
The Sandy Bridge BWG and the Sandy Bridge UEFI reference code do not
disable the MTRR on the XiP, allowing the CPU to run at full speed
when setting up CAR. On UEFI the CAR is set up by touching each
cache-line once. It doesn't clear the CAR while doing so.
Do the same to speed up setting CAR:
- Invalidate the cache
- Enable the SPI ROM XiP MTRR
- Set CR0.CD=0
- Touch one spot in each cache-line
- Clear CAR after NEM has been set up
To ensure that the CAR MTRR area is 64-byte aligned add an ALIGN to
the linker script. All existing boards should use a 64-byte alignment
for CAR.
TEST=Booted on Lenovo X220 and measured with cbmem -t:
TODO: Test on platforms that have FSRM (Ivy Bridge and newer).
Before:
0:1st timestamp 1,083 (0)
11:start of bootblock 93,765 (92,681)
After:
0:1st timestamp 0
11:start of bootblock 24,027
Boots 69msec faster than before or about 4 times faster.
Change-Id: Ia8baef28fd736ef6bb02d8a100d752ac0392e1cf
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88792
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This makes the code easier to follow.
Change-Id: I5a4b7fe99875a1addf611f569990ff9a3beda3ba
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74800
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Only 3 bytes should be used for the reset vector and it looks like
modern tooling has no problem with using a regular relative jump
instruction.
TESTED: Qemu Q35 still boots fine.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ie371000c60d66c032a8dcccb98e7627df09d3aa4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Extracted ICR wait logic into a new function 'icr_wait_timeout'.
Change-Id: Ie48899f7afb125061fd7efd44c83f5775c05d254
Signed-off-by: NyeonWoo Kim <knw0507@naver.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Cover the SPIROM with a temporary MTRR to speed up SPI flash accesses
after MPinit has removed the MTRR that was installed for postcar stage.
TEST=Booted on Lenovo X220 and measured using cbmem -t:
Before:
16:finished LZMA decompress (ignore for x86) 1,391,520 (366,351)
After:
16:finished LZMA decompress (ignore for x86) 1,218,418 (210,054)
Boots 156msec faster than before.
Change-Id: Ia3df06b5c2a09e05c76361f3e38be83475122ee7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88811
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently .bss and .data are within the PT_LOAD area of the
bootblock.elf and thus are placed and initialized at the correct spot
when PSP loads the BIOS Reset Image into DRAM.
On S3 resume PSP verifies that the "BIOS Reset Image" is unmodified
before it hands over control to such. Due to the use of BSS and DATA
within the BIOS Reset Image and the modifications of such at previous
boot the verification always fails.
This change moves '.bss' and '.data' out of the *first* PT_LOAD area
and moves it into a separate data_segment also marked PT_LOAD. Since
the second PT_LOAD is ignored by AMDCOMPRESS it doesn't end in the area
being verified at S3 resume. Since '.data' is now part of a separate
PT_LOAD a new region is inserted called '.datacopy' which is filled
by using objcopy. In turn the assembly code in bootblock will memcpy
'.datacopy' to '.data'.
TEST: Can still boot on amd/birman+ and on up/squared.
Change-Id: Id159ade3029060ce2ca6abcb723d5bdfe8841c3a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
The PCODE mailbox is primarily used by CPU code in ramstage. However,
it is also used as part of enabling DDR 2x refresh rate, which is now
implemented in coreboot as part of NRI (native RAM init).
The PCODE mailbox functions in CPU code were not exported at the time
NRI was being developed, so I chose to temporarily copy the functions
into NRI code to make it easier to rebase NRI patches since it avoids
potential merge conflicts. After a few years of rebasing patches, NRI
finally got submitted, so there's no reason to keep duplicate code in
the tree anymore.
Put the relevant PCODE functions into a new file, which gets compiled
for both ramstage (CPU init) and romstage (NRI). The BCLK calibration
function is only used in ramstage so there's no need to move it.
Change-Id: I340625fabc072139b8def254f1ce6b19f360adcd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Group entries by stage and sort groups by stage execution order.
Change-Id: I6e2a53d6555700b48fd3aececdfdb8983554a75a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
If the directory specified by CONFIG_CPU_INTEL_UCODE_SPLIT_BINARIES does
not contain any files, no build error will occur, and resulting coreboot
image will not include any microcode.
BUG=None
TEST="src/cpu/intel/microcode/Makefile.mk:16: *** "microcode-params is
empty. Ensure CONFIG_CPU_INTEL_UCODE_SPLIT_BINARIES is set correctly and
contains valid files.". Stop."
Change-Id: I095d9a24cb473b528d85bf8325c06fd3dc055b74
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87636
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
In order to give SMM access to more than 4GiB on x86_64, update the
page table generation in the SMM loader.
Honor CONFIG_CPU_PT_ROM_MAP_GB and map the same amount of the address
space as done in other stages. This is required for SMM trying to access
the SPI BAR in high MMIO on AMD platforms.
TEST=Could access ROM3 BAR at 0xfd00000000 in SMM on AMD/birman+
Change-Id: Iae3dac8d39d3f5e55cc08aa96c8924f6364c5140
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87573
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
To avoid confusion drop the label smm_handler_start, since it's unused
and the same name is also used in the permanent handler as C entry point
(see smm_module_handler.c).
Change-Id: I22bb5d378e8848d526f897cb2de70c0221827d0d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87554
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
This change refactors MTRR handling by consolidating helper functions
from `earlymtrr.c` and `mtrr.c` into a new MTRR library (`mtrrlib`).
This approach improves code modularity and reusability, making these
utilities consistently available across different coreboot boot phases.
The following functions are now part of `mtrrlib`:
- `get_free_var_mtrr`: Retrieves the index of the first available
variable MTRR.
- `set_var_mtrr`: Configures the variable MTRR, specified by an `index`,
for a memory region defined by `base`, `size`, and `type`.
- `clear_var_mtrr`: Disables the variable MTRR at a given index.
- `acquire_and_configure_mtrr`: Acquires a free variable MTRR, configures
it with the given `base`, `size`, and `type`.
BUG=b:409718202
TEST=Built and booted google/fatcat successfully.
Change-Id: Iba332b7088221fd930e973fad9410833bff184b9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87539
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Currently there are 3 GDTs (Global Descriptor Tables) being used on x86:
- preRAM (gdt_init.S)
- SMM (smm_stub.S)
- RAM (c_start.S)
They have different layouts and thus different offsets for the segments
being used in assembly code. Stop using different GDT segments and
ensure that for ROM (preRAM + SMM) and RAM (ramstage) the segments
match. RAM will have additional entries, not found in pre RAM GDT,
but the segments for protected mode and 64-bit mode now match in
all stages.
This allows to use the same defines in all stages. It also drops the
need to know in which stage the code is compiled and it's no longer
necessary to switch the code segment between stages.
While at it fix the comments in the ramstage GDT and drop unused
declarations from header files, always set the accessed bit and drop
GDT_CODE_ACPI_SEG.
Change-Id: I208496e6e4cc82833636f4f42503b44b0d702b9e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Add an exception handler to SMM to debug crashes when a serial
console is enabled and DEBUG_SMI is set. This allows for narrowing
down issues faster than letting the machine triple fault.
Change-Id: I2ccaf8d23d508d773ce56912983884ad6832ede6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
The GNU assembler allows to use arithmetics on constant expression,
except for division using the '/' character. By default the '/'
introduces a line comment, see [1]. This behaviour can be changed when
the command line argument --divide is being used. However that's not
the case for coreboot.
Since the divide doesn't work as expected the assembler generates 512
times as much instructions on the .rept evaluation than it should. This
didn't cause any problem since it only filled PML4E, but the additional
entries pointed to non existing PDPTs. As long as the memory above 512GB
wasn't accessed it worked just fine.
Use shifts to fix the arithmetic and thus generate only the expected
number of page table entries. Required for the following patch, which
walks page tables and expects to find sane directories.
1: https://sourceware.org/binutils/docs-2.26/as/i386_002dChars.html#i386_002dChars
TEST=GAS generates 512 times less entries on .rept evaluation
Change-Id: I480142df010bf4e7d6fb84c9891e93b6ee21e908
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87356
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The parameter CPU isn't used, thus drop it.
Change-Id: Ie7f6179f0545f905463752e94243b438143d8234
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Stop using magic values and use defines for Global Descriptor Table
(GDT) offsets. Use the existing defines from the corresponding headers.
Change-Id: I40c15f6341bdef9cd457619ec81e7ac624ec2d63
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87254
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 4b5a490b6f.
Reason for revert: This effort was apparently given up on since 4 years.
So remove the function, since it is not used at the moment. If someone
wants to bring that effort back to live, said person can feel free to do
so.
Change-Id: I26d5c9fbfd6eae24f876d857a6e952ca0d1a64ae
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The code currently unconditionally flushes or invalidates the entire
cache (using `clflush_region` or `wbinvd`) after loading the SIPI vector
for APs and after loading SMM handlers.
This commit modifies this behavior to only perform these cache
operations if the CPU does *not* support self-snooping.
Self-snooping CPUs can maintain cache coherency within the core/
complex more efficiently. CPU with self-snoop enabled does not
necessarily need to perform wbinvd to ensure data written to the
cache is reflected in main memory. Self-snooping CPUs employ a
write-back caching policy, combined with a cache coherence protocol,
to manage data writes and ensure consistency between cache and main
memory.
When the BSP writes the SIPI vector or SMM handlers to memory, other
units within the same CPU that might be caching these regions should
be aware of the updates through the self-snooping mechanism. A full
cache flush or invalidate to ensure cache contains reaches to main
memory might be unnecessary and could negatively impact performance.
By conditionally performing these cache operations based on
`self_snooping_supported()`, we can optimize the boot process for CPUs
that have advanced cache coherency features while maintaining correct
behavior on older or simpler CPUs.
TEST=Boot google/rex, brox and fatcat with this patch. Able to reduce
boot time by ~19-25ms.
Change-Id: If32439752d0ceaa03b1d81873ea0bc562092e9d5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87182
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
AMD64 spec refers to the field as MT (Message Type), but the IA64 spec
refers to it as DM (Delivery Mode). The problem is that there is another
field abbreviated as DM (Destination Mode) right next to it. So for
better readability, just stick to the AMD64 terminology.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I25cf69d555fe22526f128ff7ed41f82b71f2acf2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
mtrr_use_temp_range() is used to temporarily cache the area(s) of RAM
to which the SPI flash is mapped, in order to speed up reading the
payload out of flash in preparation for execution. On systems with more
than 32GiB of RAM, there are not enough MTRRs available to map the
"permanent" regions below 4GiB, these temporary regions below 4GiB, and
any RAM above 4GiB due to fragmentation in the various ranges, as well
as limitations on the area covered by a single MTRR due to how they
are stored in the CPU registers.
As a workaround, if the number of MTRRs needed for the temporary map
exceeds the maximum available for the system, retry calc_var-mtrrs()
with `above4gb` set to false.
TEST=build/boot starlabs/starbook_mtl with > 32GB RAM, verify temporary
MTRRs are able to be assigned via cbmem console log, and no boot delays
in payload loading/decompression due to the SPI flash not being cached.
Change-Id: Ia9f9a1537e7e0c2f7ce21067eceb1549d0f9ea5b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
calc_var_mtrrs() calculates the number of MTRRs needed for both WB and
UC default memory types, and returns the type that uses fewer MTRRs.
Modify it to return the number of MTRRs used as well, and if that
count exceeeds the number available on the system, throw an error
and skip calling prepare_var_mtrrs() as we know it will fail.
TEST=tested with rest of patch train
Change-Id: I2be7c5b3385731f4dc9ef62de15dcf6d4cceb5d3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86955
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
No need for this to be a signed or unsigned int.
TEST=tested with rest of patch train.
Change-Id: I409c04b928211e0e89eec324fdf3fa3997c73576
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86942
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
haswell_is_ult() returns CONFIG(INTEL_LYNXPOINT_LP) which is a boolean,
so use boolean instead of int.
Change-Id: I3c98ee819fc937ed6da9ee1340c2af10cec19eb3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
