This code has been tested on dbe62, and builds for qemu as well.
the next step is testing on simnow.
k8.h: add more prototypes and some required inline functions.
cpu.h: same
serengeti: expand defines in mainboard.h, though we need a better
mechanism; continue to fix initram.c, add new support files to Makefile
lib/console.c: include globalvars.h
lib/lar.c: Provide more informative print as the lar is scanned.
k8 north: needed reset_test.c from v2, fixes to raminit.c
arch/x86
Kconfig: new CONFIG variable CBMEMK, meaning coreboot mem k, memory
used for coreboot.
init_cpus.c: functions to start up CPUs
stage1_mtrr.c: bring over early mtrr support from v2.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@847 f3766cd6-281f-0410-b1cd-43a5c92072e9
what you get are warnings.
There is lots of room for improvement as we move to all CAR
code, but that will take time.
I hope to get this to really compile over the weekend.
At the same time, if anybody wants to take a crack at it, your efforts
are welcome.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@843 f3766cd6-281f-0410-b1cd-43a5c92072e9
processor BIST is nonzero. Checking it in initram makes no sense. Having
it as global variable is unnecessary as well. Link BIST is an entirely
different animal.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@834 f3766cd6-281f-0410-b1cd-43a5c92072e9
We need the sys_info struct in the global variables struct for
cache as ram on k8. The sys_info struct is generally very useful
so it makes sense to start accomodating it.
This patch adds an (empty for now) sys_info struct for geode.
It add sys_info to the global variables struct.
It removes global variables from console.h to a new file,
globalvars.h. Very little code needs to include this file.
This patch is tested on the dbe62 and simnow with no problems.
k8 compilation is now broken but I'm working on it. I'm going through
the eyeballs-bleed code on k8 startup to document it and with any luck
we'll have more functionality by the end of today. But it's hard ...
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@828 f3766cd6-281f-0410-b1cd-43a5c92072e9
current compilation unit to be marked as externally_visible. We have
EXPORT_SYMBOL exactly for that purpose.
This applies to the following symbols used by x86emu and/or vm86:
- pci_read_config8
- pci_read_config16
- pci_read_config32
- pci_write_config8
- pci_write_config16
- pci_write_config32
- dev_find_pci_device
- dev_find_slot
It also applies to the main entry point of stage2:
- stage2
With this patch, I can use -fwhole-program for stage2 without any
problems. For standard compilation, this is a noop.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@827 f3766cd6-281f-0410-b1cd-43a5c92072e9
This means that basic resource maps are working, initial hypertransport
setup is working, the amd8111 ISA device is working, config space is
working for all the parts, we can grow the FLASH part address space to
more than 64k, and in general we're having a good time.
Here is the output:
coreboot-3.0.824 Tue Aug 26 22:18:21 PDT 2008 starting...
(console_loglevel=8)
Choosing fallback boot.
LAR: Attempting to open 'fallback/initram/segment0'.
LAR: Start 0xfff80000 len 0x80000
LAR: normal/option_table@0xfff80000, size 1776
LAR: normal/initram/segment0@0xfff80740, size 24404
LAR: normal/stage2/segment0@0xfff866f0, size 1
LAR: normal/stage2/segment1@0xfff86750, size 18542
LAR: normal/stage2/segment2@0xfff8b010, size 559
LAR: normal/payload/segment0@0xfff8b290, size 18142
LAR: bootblock@0xffff7fc0, size 32768
LAR: File not found!
LAR: Run file fallback/initram/segment0 failed: No such file.
Fallback failed. Try normal boot
LAR: Attempting to open 'normal/initram/segment0'.
LAR: Start 0xfff80000 len 0x80000
LAR: normal/option_table@0xfff80000, size 1776
LAR: normal/initram/segment0@0xfff80740, size 24404
LAR: CHECK normal/initram/segment0 @ 0xfff80740
start 0xfff80790 len 24404 reallen 24404 compression 0 entry 0x00000004
loadaddress 0x00000000
Entry point is 0xfff80794
Hi there from stage1
stage1 returns
run_file returns with 0
Goal for tomorrow is to get initram done.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@826 f3766cd6-281f-0410-b1cd-43a5c92072e9
image, and fails:
LAR build/coreboot.rom
Bootblock coreboot.bootblock does not appear to be a bootblock.
Error adding the bootblock to the LAR.
make: *** [/home/rminnich/src/bios/coreboot-v3/build/coreboot.rom] Error
1
Next step is to get rid of all warnings that are not #warning.
Then it is on to simnow.
Anyone who wants to work on the warnings is most welcome to.
DBE62 still builds with no problems.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@808 f3766cd6-281f-0410-b1cd-43a5c92072e9
Geode still builds fine.
include/lib.h includes a new function, cycles(), which is a u64 and
architecture-defined. (Thanks, Plan 9, for a sensible idea).
All rdtsc removed in favor of cycles()
All other changes are k8 specific. None of these changes adversely
impact existing platforms AFAICT.
Goal is that by 31/8/8, we're testing on simnow.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@807 f3766cd6-281f-0410-b1cd-43a5c92072e9
Continue to upgrade northbridge for k8.
Add a new standard include (which is optional on some chipsets),
mainboard.h, which will define important mainboard constants that
1. do not belong in dts
2. do not belong in Kconfig
3. are so tightly tied down to the mainboard they should probably not be
visible, i.e. the value of the variable is defined by artwork on the
mainboard, such as the socket type.
This file resolves the long-standing question of where certain
mainboard-dependent, compile-time control variables belong.
We've not resolved this issue in two years so here's how
we're going to do it. The first use of this is in the definition of
CPU_SOCKET_TYPE, needed by the northbridge code.
These changes do not affect existing Geode builds (tested on DBE62).
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@792 f3766cd6-281f-0410-b1cd-43a5c92072e9
It's all REV_F now and we're wasting time pretending otherwise. This
change simplifies the code and will continue to simplify the code.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@788 f3766cd6-281f-0410-b1cd-43a5c92072e9
existing code does not work due to the characteristics of stage1. This
has been broken since r729.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@786 f3766cd6-281f-0410-b1cd-43a5c92072e9
code now unconditionally pushes an empty pointer to the stack which is a
placeholder for the pointer to global variable storage. That pointer and
the global variable storage are initialized in global_vars_init().
Creating global variables is now a piece of cake. You don't even have to
touch any asm code, just add them to struct global_vars.
Build tested on all targets, boot tested on Qemu.
NOTES:
- The code is not yet MP safe, but that's due to v3 not being MP safe in
general (and the comments contradict the code regarding MP features).
- K8 code now works by accident.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Segher Boessenkool <segher@kernel.crashing.org>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@785 f3766cd6-281f-0410-b1cd-43a5c92072e9
Added a stepping enum to k8.h. This will allow us to do things like this:
if (cpu_stepping(node) < E0)
and so on instead of is_cpu_pre_e0_in_bsp or whatever it is.
Added and fixed Kconfig variables.
Broke out northbridge by function, so we can see what goes with what.
This tree still builds a working DBE62 coreboot that boots a kernel; no harm done to existing ports.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@781 f3766cd6-281f-0410-b1cd-43a5c92072e9
not that readable anyway, so kill them and use standard definitions
instead.
Introduce EXPORT_SYMBOL for shared symbols. EXPORT_SYMBOL tells the
compiler to use the standard calling conventions for a given symbol and
not to optimize it away.
Benefits:
- We can later use gcc -combine -fwhole-program without problems.
- It's a correctness fix for some optimizations.
- We could check for duplicated exported functions at link time.
- We could check whether exported functions are linked into initram or
stage2 by accident.
- We could generate usage statistics and possibly optimize away unused
shared functions.
- Through the above points, significant side reductions of 10-40%
Build and boot tested on qemu.
Build tested on all targets.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@780 f3766cd6-281f-0410-b1cd-43a5c92072e9
Calling non-PIC code from PIC code needs an ABI wrapper and we don't
provide one. Our trick with function pointers is exceedingly fragile:
- it depends on gcc not being clever enough
- it forces us to compile all initram source files in one go
- parallelizing initram compilation breaks the code
- compiling one initram source file at a time breaks the code
- enabling higher optimizations breaks the code
- enabling -fwhole-program breaks the code
- declaring the function pointers const breaks the code
- it's an undocumented side effect of gcc which will go away
- we need excessively ugly shared function wrappers
- the shared function wrappers had more than their fair share of bugs
- almost nobody understands the wrappers completely
- Segher warns against them: "So why do you think this should work?
You're telling it to link PIC to non-PIC. Did you read the manual? It's
just not allowed. It cannot ever work."
Kill the SHARED wrappers and use a real ABI wrapper.
The wrapper code is autogenerated on demand.
Any function compiled into stage0 is now shared by default, yet the size
and code generation of stage0/1/2 code are unchanged. Initram code size
does decrease quite a bit and the difficulty of creating shared
functions is now zero.
The patch includes extensive documentation about the inner workings of
the new wrappers and the reasons why they look like this.
Build and boot tested on qemu.
Build tested on all targets.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Ron says:
Wow. we've need this fix for a long time.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@775 f3766cd6-281f-0410-b1cd-43a5c92072e9
printk buffer management to it.
Build tested and boot tested and result tested on Qemu.
Adding a new global variable is not as easy as it looks, but the
comments in the code should be good enough to tell you how.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@760 f3766cd6-281f-0410-b1cd-43a5c92072e9
all stages, blighting everything with the same code, compiled different
ways. In this change, we see that:
- basic conf ops are compiled into stage0, where they are used.
- they are called directly from initram
- they are used to initialize the pci_cf8_conf1 structure in stage 2,
but the call still goes to stage0!
one copy of the code.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@752 f3766cd6-281f-0410-b1cd-43a5c92072e9
The option code is tricky as it is used by standalone code. If you
include that file and you are standalone, you now have to define
STANDALONE (is there a better way?)
Change the cpuid to be a 24-byte string instead of 3 u32s.
Make the CPUID usage PIC-safe by not using %ebx.
Test building on two different geodes, tested to boot on dbe62
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@750 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@745 f3766cd6-281f-0410-b1cd-43a5c92072e9
This includes using consistent (C) lines, adding email addresses,
and so on. The file southbridge/nvidia/mcp55/dts was never edited
by Yinghai Lu (thus removing his (C) line) and would be too trivial
anyway...
The changes (though trivial) were also informally acked by Ron on IRC.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@744 f3766cd6-281f-0410-b1cd-43a5c92072e9
readability. Move to anonymous unions.
Build tested on all targets. Boot tested on qemu.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Ron tested this and it boots to Linux.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@730 f3766cd6-281f-0410-b1cd-43a5c92072e9
(1)we now compile in all printks, which is good: we can print any message provided we can change
the console log level at any time.
(2) The console log level is compiled in and unchangeable, which is bad, as it defeats the purpose of (1).
Add a BIOS_ALWAYS log level. Make console log level a variable. Make functions that set it and get it
visible everywhere. Always print out the version message; this is really *not* noise!
PCI: Simplify pci functions so that they can be used in stage1 or anywhere for that matter. Add
a find function which is needed for many stage1 functions. Note that we copy but also clean up
the libpayload stuff just a bit.
Get rid of config space type 2. If there was ever a platform that used it, I don't know what it was,
and the presence is a needless distraction.
tested and working on DBE62 (which means the console and the pci functions work :-).
There is a remaining problem with dumplxmsrs which nobody understands. It prints out garbage if we use the
%s for the msr names.
Formatting is an issue; if somebody wants to fix formatting they can assume I will ack it. Sorry,
my emacs has gone just nuts.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@729 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@722 f3766cd6-281f-0410-b1cd-43a5c92072e9
Resource map and a way to use the pci config stuff from stage 1, done in
a way that will work in stage 2 (but only for systems that use type 1
config cycles; will fail for type MEM config cycles).
We need to rethink the PCI config stuff per Stepan's comment, in part
because the device tree now includes things that are NOT PCI devices.
Stepan's suggestion, to make the functions take busdevfn as the
parameter, makes a lot of sense.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.s
git-svn-id: svn://coreboot.org/repository/coreboot-v3@720 f3766cd6-281f-0410-b1cd-43a5c92072e9
it working, then we'll get it pretty.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@717 f3766cd6-281f-0410-b1cd-43a5c92072e9
This is not nearly complete, but just the current state of my tree.
k8/raminit.c does not compile at all. Lots of fixes are still needed to bring
it working into v3. I've gone through about 1/8 of the file, it errors out on
line 576 now.
The mcp55 files are in a very early state and also do not compile for me, so
I've disabled them by commenting out the select in mainboard/gigabyte/Kconfig.
Once northbridge/amd/k8/raminit.c builds, k8_ops needs to be added, then we
may actually see the first v3 k8 build. :)
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@713 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@706 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@702 f3766cd6-281f-0410-b1cd-43a5c92072e9
parameter to two functions.
2. geodelx.h: define DRAM_TERMINATED and DRAM_UNTERMINATED constants
3. dbe62/initram.c: move to auto PLL control, so set MANUALCONF to 0
4. all other initram.c: set up calls to cpu_reg_init with proper
TERMINATED/UNTERMINATED constants.
builds for dbe62. The auto PLL strapping is tested and works.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@699 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@698 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-Off-By: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@691 f3766cd6-281f-0410-b1cd-43a5c92072e9
changed during run time. (trivial patch)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@651 f3766cd6-281f-0410-b1cd-43a5c92072e9
This includes:
- the working power button patch.
- onchipuart2 for very early startup -- this will be replaced with a better mechanism soon.
- dts mod for powerbutton on cs5536
- dbe62 dts fix for COM1 setup
- ram check call in dbe62 initram.c
- Carl-Daniel's fix to detect incorrect access to spd variables.
- more debug prints in geodelx northbridge support code.
This is cumulative since we're lagging on acks a bit and it's hard to keep this
stuff all seperated out since it involves a common set of files. I'd like to get
it acked and in tree today if possible. It's a very small set of lines changed so please
forgive me for the cumulative nature.
Thanks
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@636 f3766cd6-281f-0410-b1cd-43a5c92072e9
Note: You MUST have the later AMD VSA code that does not call bios
interrupts. If you use the older code, your boot will hang at this
point:
buf[0x20] signature is b0:10:e6:80
Call real_mode_switch_call_vsm
With post code 10
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@616 f3766cd6-281f-0410-b1cd-43a5c92072e9
before they can be #included. That is completely counter-intuitive. Add
necessary #includes to the header files themselves.
Fix a few cases where nonexisting files were #included.
Compile tested on Qemu and Alix1C.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@611 f3766cd6-281f-0410-b1cd-43a5c92072e9
number during boot.
Convert process_file() to use enum compalgo instead of hardcoded
"1","2","3" and change the control structure from a series of if()
statements to a switch() statement.
Uppercasing enum compalgo also found a name clash between NONE as
compression algo and NONE as operation mode of util/lar.
Compile and boot tested on Qemu.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@606 f3766cd6-281f-0410-b1cd-43a5c92072e9
code boots and works on qemu and
alix1c. It represents a huge change and a huge improvement. There are a
few fixes left to do, which
will come once this is in.
This change started out easy: get the device IDs OUT of the the dts, and
into one place. We
decided the device IDs should be in the constructors ONLY. To make a
long story short, that just did
not work out, and it revealed a flaw in the design. The result?
- no more ids in the various dts files.
- the constructor struct is gone -- one less struct, nobody liked the
name anyway
- the device_operations struct now includes the device id.
- constructor property no longer used; use device_operations instead.
- lpc replaced with ioport
All the changes below stem from this "simple" change.
I am finding this new structure much easier to work with. I hope we're
done
on this for real, however!
TODO:
1. Change limitation in dtc that makes it hard to use hex in pci@
notation.
Now for the bad news. Sometime today, interrupts or io or something
stopped working between r596 and r602 -- but I did no commits at
that point. So something has gone wrong, but I don't think it's this
stuff.
I did try a build of HEAD, and it fails really, really badly. Much
more badly than this fails, so I think this commit is only going
to improve things. It does work fine on qemu, fails on alix1c,
so I suspect one of today's "clean up commits" broke something.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@603 f3766cd6-281f-0410-b1cd-43a5c92072e9
for this is that currently, if you select no compression, the bss
segment of filo takes up 153K with just zeroes. With this patch, it
always takes up a lar header + 1 byte. I left the one byte so that
the checksum wouldn't be broken.
This patch could have taken out the calloc in the compression area,
but since it only uses compile-time memory, I decided to keep this
simple.
Myles
Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@601 f3766cd6-281f-0410-b1cd-43a5c92072e9
CONFIG_* == 1. If those variables are set, they will always be 1.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@599 f3766cd6-281f-0410-b1cd-43a5c92072e9
in dts. This gets rid of the ugly pcipath etc. properties.
So, instead of
somedevice {pcipath="1,0";};
We say pci@1,0{ etc. etc. };
As per my agreement I agree to document this in the design doc.
The alix1c compiles but is untested, and will probably need some work.
I will do these additional tasks on friday.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
M include/device/path.h
Add LPC path type, replacing SUPERIO path type, since SUPERIO is only
one type of LPC. Clean up tabbing in parts of the file (cosmetic).
M mainboard/emulation/qemu-x86/dts
Modify this dts for the new path naming scheme.
M device/pci_device.c
Change what used to be a BIOS_ERR (but is no longer) to a BIOS_NOTICE.
The change is that the device tree includes more than just PCI devices,
so finding a non-PCI device is no longer fatal; a notice is useful.
M device/device_util.c
Add string creation for PCI_BUS nad LPC.
M northbridge/intel/i440bxemulation/dts
Add ID info for the chip.
M northbridge/intel/i440bxemulation/i440bx.c
Change initialization so it is explicitly for the .ops struct member.
M util/dtc/flattree.c
Add support for the new path naming scheme.
I'm in the middle of this commit so I'll fix the hard-coded lengths
next commit.
Also delete dead code between #if 0 and /* and //
M util/x86emu/vm86.c
comment out unused variables. these may someday be use, not ready
to delete them yet.
M Makefile
Change -O2 to -g. We need debugging on LAR far more than we need performance.
git-svn-id: svn://coreboot.org/repository/coreboot-v3@593 f3766cd6-281f-0410-b1cd-43a5c92072e9
