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1. geodelx.c: cover case of unterminated DRAM by adding a terminated

Browse source 
parameter to two functions. 
2. geodelx.h: define DRAM_TERMINATED and DRAM_UNTERMINATED constants
3. dbe62/initram.c: move to auto PLL control, so set MANUALCONF to 0
4. all other initram.c: set up calls to cpu_reg_init with proper 
   TERMINATED/UNTERMINATED constants. 

builds for dbe62. The auto PLL strapping is tested and works. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@699 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich 2008-07-29 15:54:46 +00:00
commit 96914e1655
9 changed files with 23 additions and 13 deletions
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13
arch/x86/geodelx/geodelx.c
View file

@ -313,8 +313,9 @@ static const struct delay_controls {
*
* @param dimm0 The SMBus address of DIMM 0 (mainboard dependent).
* @param dimm1 The SMBus address of DIMM 1 (mainboard dependent).
* @param terminated The bus is terminated. (mainboard dependent).
*/
static void set_delay_control(u8 dimm0, u8 dimm1)
static void set_delay_control(u8 dimm0, u8 dimm1, int terminated)
{
u32 glspeed;
u8 spdbyte0, spdbyte1, dimms, i;
@ -376,7 +377,10 @@ static void set_delay_control(u8 dimm0, u8 dimm1)
spdbyte0 += spdbyte1;
for (i = 0; i < ARRAY_SIZE(delay_control_table); i++) {
if ((dimms == 1) && (terminated == DRAM_TERMINATED)) {
msr.hi = 0xF2F100FF;
msr.lo = 0x56960004;
} else for (i = 0; i < ARRAY_SIZE(delay_control_table); i++) {
if ((dimms == delay_control_table[i].dimms) &&
(spdbyte0 <= delay_control_table[i].devices)) {
if (glspeed < 334) {
@ -400,8 +404,9 @@ static void set_delay_control(u8 dimm0, u8 dimm1)
* setting in future.
* @param dimm0 SMBus address of DIMM 0 (mainboard dependent).
* @param dimm1 SMBus address of DIMM 1 (mainboard dependent).
* @param terminated The bus is terminated (mainboard dependent).
*/
void cpu_reg_init(int debug_clock_disable, u8 dimm0, u8 dimm1)
void cpu_reg_init(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated)
{
struct msr msr;
@ -432,7 +437,7 @@ void cpu_reg_init(int debug_clock_disable, u8 dimm0, u8 dimm1)
wrmsr(GLIU1_PORT_ACTIVE, msr);
/* Set the Delay Control in GLCP. */
set_delay_control(dimm0, dimm1);
set_delay_control(dimm0, dimm1, terminated);
/* Enable RSDC. */
msr = rdmsr(CPU_AC_SMM_CTL);

7
include/arch/x86/amd_geodelx.h
View file

@ -376,6 +376,11 @@
#define GLCP_DELAY_CONTROLS (MSR_GLCP + 0x0F)
#define DELAY_UPPER_DISABLE_CLK135 (1 << 23)
#define DELAY_LOWER_STATUS_MASK 0x7C0
/* DRAM_TERMINATED affects how the DELAY register is set. */
#define DRAM_TERMINATED 'T'
#define DRAM_UNTERMINATED 't'
#define GLCP_SYS_RSTPLL (MSR_GLCP + 0x14) /* R/W */
#define RSTPLL_UPPER_GLMULT_SHIFT 7
#define RSTPLL_UPPER_GLMULT_MASK 0x1F
@ -1281,7 +1286,7 @@ static inline u16 vr_read(u16 class_index)
u32 geode_link_speed(void);
void geodelx_msr_init(void);
void pll_reset(int manualconf, u32 pll_hi, u32 pll_lo);
void cpu_reg_init(int debug_clock_disable, u8 dimm0, u8 dimm1);
void cpu_reg_init(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated);
void system_preinit(void);
void msr_init(void);
void geode_pre_payload(void);

2
mainboard/adl/msm800sev/initram.c
View file

@ -50,7 +50,7 @@ int main(void)
pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO);
cpu_reg_init(0, DIMM0, DIMM1);
cpu_reg_init(0, DIMM0, DIMM1, DRAM_TERMINATED);
sdram_set_registers();
sdram_set_spd_registers(DIMM0, DIMM1);
sdram_enable(DIMM0, DIMM1);

2
mainboard/amd/db800/initram.c
View file

@ -86,7 +86,7 @@ int main(void)
pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO);
printk(BIOS_DEBUG, "done pll reset\n");
cpu_reg_init(0, DIMM0, DIMM1);
cpu_reg_init(0, DIMM0, DIMM1, DRAM_UNTERMINATED);
printk(BIOS_DEBUG, "done cpu reg init\n");
sdram_set_registers();

2
mainboard/amd/norwich/initram.c
View file

@ -86,7 +86,7 @@ int main(void)
pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO);
printk(BIOS_DEBUG, "done pll reset\n");
cpu_reg_init(0, DIMM0, DIMM1);
cpu_reg_init(0, DIMM0, DIMM1, DRAM_TERMINATED);
printk(BIOS_DEBUG, "done cpu reg init\n");
sdram_set_registers();

2
mainboard/artecgroup/dbe61/initram.c
View file

@ -149,7 +149,7 @@ int main(void)
pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO);
printk(BIOS_DEBUG, "done pll reset\n");
cpu_reg_init(0, DIMM0, DIMM1);
cpu_reg_init(0, DIMM0, DIMM1, DRAM_UNTERMINATED);
printk(BIOS_DEBUG, "done cpu reg init\n");
sdram_set_registers();

4
mainboard/artecgroup/dbe62/initram.c
View file

@ -33,7 +33,7 @@
#include <northbridge/amd/geodelx/raminit.h>
#include <spd.h>
#define MANUALCONF 1 /* Do manual strapped PLL config */
#define MANUALCONF 0 /* Do manual strapped PLL config */
#define PLLMSRHI 0x000003d9 /* manual settings for the PLL */
#define PLLMSRLO 0x07de0080 /* from factory bios */
#define DIMM0 ((u8) 0xA0)
@ -140,7 +140,7 @@ int main(void)
pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO);
printk(BIOS_DEBUG, "done pll reset\n");
cpu_reg_init(0, DIMM0, DIMM1);
cpu_reg_init(0, DIMM0, DIMM1, DRAM_UNTERMINATED);
printk(BIOS_DEBUG, "done cpu reg init\n");
sdram_set_registers();

2
mainboard/pcengines/alix1c/initram.c
View file

@ -148,7 +148,7 @@ int main(void)
pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO);
printk(BIOS_DEBUG, "done pll reset\n");
cpu_reg_init(0, DIMM0, DIMM1);
cpu_reg_init(0, DIMM0, DIMM1, DRAM_TERMINATED);
printk(BIOS_DEBUG, "done cpu reg init\n");
sdram_set_registers();

2
mainboard/pcengines/alix2c3/initram.c
View file

@ -145,7 +145,7 @@ int main(void)
pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO);
printk(BIOS_DEBUG, "done pll reset\n");
cpu_reg_init(0, DIMM0, DIMM1);
cpu_reg_init(0, DIMM0, DIMM1, DRAM_TERMINATED);
printk(BIOS_DEBUG, "done cpu reg init\n");
sdram_set_registers();