We're getting closer. It has been pointed out that this code is not pretty. I agree. Get
it working, then we'll get it pretty. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://coreboot.org/repository/coreboot-v3@717 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich
parent
c945259136
commit
30c0db46ed
10 changed files with 192 additions and 79 deletions
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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* Copyright (C) 2006-2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -282,3 +282,124 @@
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#define NBCAP_MEMCLK_166MHZ 1
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#define NBCAP_MEMCLK_200MHZ 0
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#define NBCAP_MEMCTRL (1 << 8)
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/* resources for the routing in the northbridge. These may be family specific;
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* the were in v2.
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*/
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#define RES_DEBUG 0
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#define RES_PCI_IO 0x10
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#define RES_PORT_IO_8 0x22
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#define RES_PORT_IO_32 0x20
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#define RES_MEM_IO 0x40
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#ifndef ASSEMBLY
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/* cpu version -- no support for f0 yet */
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static inline int is_cpu_rev_a0(void)
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{
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return (cpuid_eax(1) & 0xfffef) == 0x0f00;
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}
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static inline int is_cpu_pre_c0(void)
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{
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return (cpuid_eax(1) & 0xfffef) < 0x0f48;
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}
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static inline int is_cpu_c0(void)
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{
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return (cpuid_eax(1) & 0xfffef) == 0x0f48;
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}
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static inline int is_cpu_pre_b3(void)
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{
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return (cpuid_eax(1) & 0xfffef) < 0x0f41;
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}
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static inline int is_cpu_b3(void)
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{
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return (cpuid_eax(1) & 0xfffef) == 0x0f41;
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}
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//AMD_D0_SUPPORT
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static inline int is_cpu_pre_d0(void)
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{
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return (cpuid_eax(1) & 0xfff0f) < 0x10f00;
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}
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static inline int is_cpu_d0(void)
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{
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return (cpuid_eax(1) & 0xfff0f) == 0x10f00;
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}
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//AMD_E0_SUPPORT
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static inline int is_cpu_pre_e0(void)
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{
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return (cpuid_eax(1) & 0xfff0f) < 0x20f00;
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}
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static inline int is_cpu_e0(void)
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{
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return (cpuid_eax(1) & 0xfff00) == 0x20f00;
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}
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/* note: we'd like to have this sysinfo common to all K8, there's no need to
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* have one different kind per different kind of k8 at this point.
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*/
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//#include "raminit.h"
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struct dimm_size {
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u8 per_rank; // it is rows + col + bank_lines + data lines */
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u8 rows;
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u8 col;
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u8 bank; //1, 2, 3 mean 2, 4, 8
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u8 rank;
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} __attribute__((packed));
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struct mem_info { // pernode
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u32 dimm_mask;
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struct dimm_size sz[DIMM_SOCKETS];
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u32 x4_mask;
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u32 x16_mask;
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u32 single_rank_mask;
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u32 page_1k_mask;
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// u32 ecc_mask;
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// u32 registered_mask;
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u8 is_opteron;
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u8 is_registered;
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u8 is_ecc;
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u8 is_Width128;
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u8 memclk_set; // we need to use this to retrieve the mem param
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u8 rsv[3];
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} __attribute__((packed));
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struct link_pair_st {
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struct device * udev;
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u32 upos;
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u32 uoffs;
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struct device * dev;
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u32 pos;
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u32 offs;
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} __attribute__((packed));
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struct sys_info {
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u8 ctrl_present[NODE_NUMS];
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struct mem_info meminfo[NODE_NUMS];
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struct mem_controller ctrl[NODE_NUMS];
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u8 mem_trained[NODE_NUMS]; //0: no dimm, 1: trained, 0x80: not started, 0x81: recv1 fail, 0x82: Pos Fail, 0x83:recv2 fail
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u32 tom_k;
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u32 tom2_k;
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u32 mem_base[NODE_NUMS];
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u32 cs_base[NODE_NUMS*8]; //8 cs_idx
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u32 hole_reg[NODE_NUMS]; // can we spare it to one, and put ctrl idx in it
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u8 dqs_delay_a[NODE_NUMS*2*2*9]; //8 node channel 2, direction 2 , bytelane *9
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u8 dqs_rcvr_dly_a[NODE_NUMS*2*8]; //8 node, channel 2, receiver 8
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u32 nodes;
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struct link_pair_st link_pair[16];// enough? only in_conherent
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u32 link_pair_num;
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u32 ht_c_num;
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u32 sbdn;
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u32 sblk;
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u32 sbbusn;
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} __attribute__((packed));
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#endif /* ! ASSEMBLY */
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@ -22,7 +22,7 @@
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#define HC_POSSIBLE_NUM 8
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struct amdk8_sysconf_t {
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struct amdk8_sysconf{
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//ht
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unsigned nodes;
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unsigned hc_possible_num;
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@ -155,33 +155,32 @@
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#define PCI_VENDOR_ID_CIRRUS 0x1013
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#define PCI_DEVICE_ID_CIRRUS_5446 0x00b8 /* Used by QEMU */
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#define PCI_VENDIR_ID_NVIDIA 0x10de
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/*
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0360MCP55 LPC Bridge
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0361MCP55 LPC Bridge
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0362MCP55 LPC Bridge
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0363MCP55 LPC Bridge
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0364MCP55 LPC Bridge
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0365MCP55 LPC Bridge
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0366MCP55 LPC Bridge
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0367MCP55 LPC Bridge
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0368MCP55 SMBus
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0369MCP55 Memory Controller
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036aMCP55 Memory Controller
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036bMCP55 SMU
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036cMCP55 USB Controller
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036dMCP55 USB Controller
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036eMCP55 IDE
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0370MCP55 PCI bridge
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0371MCP55 High Definition Audio
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0372MCP55 Ethernet
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0373MCP55 Ethernet
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0374MCP55 PCI Express bridge
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0375MCP55 PCI Express bridge
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0376MCP55 PCI Express bridge
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0377MCP55 PCI Express bridge
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0378MCP55 PCI Express bridge
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037aMCP55 Memory Controller
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*/
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#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIBRIDGE 0x370
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#define PCI_VENDOR_ID_NVIDIA 0x10de
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#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC 0x0360
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#define PCI_DEVICE_ID_NVIDIA_MCP55_SLAVE 0x0361
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#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_2 0x0362
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#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_3 0x0363
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#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_4 0x0364
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#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_5 0x0365
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#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_6 0x0366
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#define PCI_DEVICE_ID_NVIDIA_MCP55_PRO 0x0367
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#define PCI_DEVICE_ID_NVIDIA_MCP55_SM2 0x0368
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#define PCI_DEVICE_ID_NVIDIA_MCP55_IDE 0x036E
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#define PCI_DEVICE_ID_NVIDIA_MCP55_SATA0 0x037E
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#define PCI_DEVICE_ID_NVIDIA_MCP55_SATA1 0x037F
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#define PCI_DEVICE_ID_NVIDIA_MCP55_NIC 0x0372
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#define PCI_DEVICE_ID_NVIDIA_MCP55_NIC_BRIDGE 0x0373
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#define PCI_DEVICE_ID_NVIDIA_MCP55_AZA 0x0371
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#define PCI_DEVICE_ID_NVIDIA_MCP55_USB 0x036C
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#define PCI_DEVICE_ID_NVIDIA_MCP55_USB2 0x036D
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#define PCI_DEVICE_ID_NVIDIA_MCP55_PCI 0x0370
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#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_B_C 0x0374
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#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_E 0x0375
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#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_A 0x0376
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#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_F 0x0377
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#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_D 0x0378
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#define PCI_DEVICE_ID_NVIDIA_MCP55_HT 0x0369
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#define PCI_DEVICE_ID_NVIDIA_MCP55_TRIM 0x036A
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#define PCI_DEVICE_ID_NVIDIA_MCP55_PMU 0x036B
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#endif /* DEVICE_PCI_IDS_H */
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