This gets us back to a compiling k8 target.
This code has been tested on dbe62, and builds for qemu as well. the next step is testing on simnow. k8.h: add more prototypes and some required inline functions. cpu.h: same serengeti: expand defines in mainboard.h, though we need a better mechanism; continue to fix initram.c, add new support files to Makefile lib/console.c: include globalvars.h lib/lar.c: Provide more informative print as the lar is scanned. k8 north: needed reset_test.c from v2, fixes to raminit.c arch/x86 Kconfig: new CONFIG variable CBMEMK, meaning coreboot mem k, memory used for coreboot. init_cpus.c: functions to start up CPUs stage1_mtrr.c: bring over early mtrr support from v2. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@847 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich
parent
6fd4e56dd7
commit
ff2ddcb313
12 changed files with 450 additions and 3 deletions
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@ -171,6 +171,15 @@ config CARSIZE
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help
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This option sets the size of the area used for CAR.
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config CBMEMK
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hex
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default 0x1000 if CPU_I586
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default 0x1000 if CPU_AMD_GEODELX
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default 0x2000 if CPU_AMD_K8
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help
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This option sets the top of the memory area, in KiB,
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used for coreboot.
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config K8_HT_FREQ_1G_SUPPORT
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hex
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default 1 if CPU_AMD_K8
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@ -321,6 +321,11 @@ unsigned int init_cpus(unsigned cpu_init_detectedx,
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unsigned bsp_apicid = 0;
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unsigned apicid;
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struct node_core_id id;
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/* this is a bit weird but soft_reset can be defined in many places,
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* so finding a common
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* include file to use is a little daunting.
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*/
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void soft_reset(void);
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/*
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* MTRR must be set by this point.
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141
arch/x86/stage1_mtrr.c
Normal file
141
arch/x86/stage1_mtrr.c
Normal file
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@ -0,0 +1,141 @@
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/* we will compile this into initram since some basic prototypes differ with same names on v2. Sigh. */
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#include <mainboard.h>
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#include <config.h>
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#include <types.h>
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#include <io.h>
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#include <console.h>
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#include <globalvars.h>
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#include <lar.h>
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#include <string.h>
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#include <tables.h>
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#include <lib.h>
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#include <mc146818rtc.h>
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#include <cpu.h>
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#include <msr.h>
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#include <mtrr.h>
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void disable_var_mtrr(unsigned int reg)
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{
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/* The invalid bit is kept in the mask so we simply
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* clear the relevent mask register to disable a
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* range.
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*/
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struct msr zero;
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zero.lo = zero.hi = 0;
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wrmsr(MTRRphysMask_MSR(reg), zero);
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}
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void set_var_mtrr(
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unsigned long reg, unsigned long base, unsigned long size, unsigned long type)
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{
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/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
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/* FIXME: It only support 4G less range */
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struct msr basem, maskm;
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basem.lo = base | type;
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basem.hi = 0;
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wrmsr(MTRRphysBase_MSR(reg), basem);
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maskm.lo = ~(size - 1) | 0x800;
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maskm.hi = (1<<(CPU_ADDR_BITS-32))-1;
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wrmsr(MTRRphysMask_MSR(reg), maskm);
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}
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void set_var_mtrr_x(
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unsigned long reg, u32 base_lo, u32 base_hi, u32 size_lo, u32 size_hi, unsigned long type)
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{
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/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
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struct msr basem, maskm;
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basem.lo = (base_lo & 0xfffff000) | type;
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basem.hi = base_hi & ((1<<(CPU_ADDR_BITS-32))-1);
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wrmsr(MTRRphysBase_MSR(reg), basem);
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maskm.hi = (1<<(CPU_ADDR_BITS-32))-1;
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if(size_lo) {
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maskm.lo = ~(size_lo - 1) | 0x800;
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} else {
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maskm.lo = 0x800;
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maskm.hi &= ~(size_hi - 1);
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}
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wrmsr(MTRRphysMask_MSR(reg), maskm);
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}
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void cache_cbmem(int type)
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{
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/* Enable caching for 0 - 1MB using variable mtrr */
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disable_cache();
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set_var_mtrr(0, 0x00000000, COREBOOT_MEM_TOPK << 10, type);
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enable_cache();
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}
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/* the fixed and variable MTTRs are power-up with random values,
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* clear them to MTRR_TYPE_UNCACHEABLE for safty.
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*/
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void do_early_mtrr_init(const unsigned long *mtrr_msrs)
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{
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/* Precondition:
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* The cache is not enabled in cr0 nor in MTRRdefType_MSR
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* entry32.inc ensures the cache is not enabled in cr0
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*/
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struct msr msr;
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const unsigned long *msr_addr;
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/* Inialize all of the relevant msrs to 0 */
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msr.lo = 0;
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msr.hi = 0;
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unsigned long msr_nr;
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for(msr_addr = mtrr_msrs; (msr_nr = *msr_addr); msr_addr++) {
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wrmsr(msr_nr, msr);
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}
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#warning fix the XIP bits in stage1_mtrr.c that enable write through caching so we can do execute in place on the flash rom.
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#if 0
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#if defined(XIP_ROM_SIZE)
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/* enable write through caching so we can do execute in place
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* on the flash rom.
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*/
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set_var_mtrr(1, XIP_ROM_BASE, XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
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#endif
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#endif
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/* Set the default memory type and enable fixed and variable MTRRs
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*/
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/* Enable Variable MTRRs */
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msr.hi = 0x00000000;
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msr.lo = 0x00000800;
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wrmsr(MTRRdefType_MSR, msr);
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}
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void early_mtrr_init(void)
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{
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static const unsigned long mtrr_msrs[] = {
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/* fixed mtrr */
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0x250, 0x258, 0x259,
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0x268, 0x269, 0x26A,
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0x26B, 0x26C, 0x26D,
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0x26E, 0x26F,
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/* var mtrr */
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0x200, 0x201, 0x202, 0x203,
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0x204, 0x205, 0x206, 0x207,
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0x208, 0x209, 0x20A, 0x20B,
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0x20C, 0x20D, 0x20E, 0x20F,
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/* NULL end of table */
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0
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};
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disable_cache();
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do_early_mtrr_init(mtrr_msrs);
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enable_cache();
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}
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int early_mtrr_init_detected(void)
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{
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struct msr msr;
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/* See if MTRR's are enabled.
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* a #RESET disables them while an #INIT
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* preserves their state. This works
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* on both Intel and AMD cpus, at least
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* according to the documentation.
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*/
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msr = rdmsr(MTRRdefType_MSR);
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return msr.lo & 0x00000800;
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}
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@ -690,6 +690,76 @@ void set_apicid_cpuid_lo(void);
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void enable_fid_change(void);
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void init_fidvid_bsp(unsigned bsp_apicid);
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/* k8/northbridge.c */
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void sdram_initialize(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo);
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/* k8/reset_test.c */
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void distinguish_cpu_resets(unsigned nodeid);
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/* These are functions that MUST be inlined as we can not use a stack -- CAR or real ram */
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/* by yhlu 6.2005 */
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/* be warned, this file will be used other cores and core 0 / node 0 */
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static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
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{
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__asm__ volatile (
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/* We don't need cache as ram for now on */
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/* disable cache */
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"movl %cr0, %eax\n\t"
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"orl $(0x1<<30),%eax\n\t"
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"movl %eax, %cr0\n\t"
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/* clear sth */
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"movl $0x269, %ecx\n\t" /* fix4k_c8000*/
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"xorl %edx, %edx\n\t"
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"xorl %eax, %eax\n\t"
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"wrmsr\n\t"
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#if CONFIG_CARSIZE > 0x8000
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"movl $0x268, %ecx\n\t" /* fix4k_c0000*/
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"wrmsr\n\t"
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#endif
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/* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/
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"movl $0xC0010010, %ecx\n\t"
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// "movl $SYSCFG_MSR, %ecx\n\t"
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"rdmsr\n\t"
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"andl $(~(3<<18)), %eax\n\t"
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// "andl $(~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn)), %eax\n\t"
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"wrmsr\n\t"
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/* Set the default memory type and disable fixed and enable variable MTRRs */
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"movl $0x2ff, %ecx\n\t"
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// "movl $MTRRdefType_MSR, %ecx\n\t"
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"xorl %edx, %edx\n\t"
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/* Enable Variable and Disable Fixed MTRRs */
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"movl $0x00000800, %eax\n\t"
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"wrmsr\n\t"
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/* enable cache */
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"movl %cr0, %eax\n\t"
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"andl $0x9fffffff,%eax\n\t"
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"movl %eax, %cr0\n\t"
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);
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}
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static void disable_cache_as_ram_bsp(void)
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{
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__asm__ volatile (
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// "pushl %eax\n\t"
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"pushl %edx\n\t"
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"pushl %ecx\n\t"
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);
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disable_cache_as_ram();
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__asm__ volatile (
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"popl %ecx\n\t"
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"popl %edx\n\t"
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// "popl %eax\n\t"
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);
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}
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#endif /* ! ASSEMBLY */
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#endif /* AMD_K8_H */
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@ -21,10 +21,11 @@
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#ifndef ARCH_X86_CPU_H
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#define ARCH_X86_CPU_H
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#include <config.h>
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#include <types.h>
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#include <device/device.h>
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#include <shared.h>
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#include <mtrr.h>
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#define X86_VENDOR_INTEL 0
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#define X86_VENDOR_CYRIX 1
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@ -81,6 +82,13 @@ struct cpuinfo_x86 {
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u8 x86_mask;
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};
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/* prototypes for functions that may or may not be compiled in depending on cpu type */
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void set_var_mtrr_x(
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unsigned long reg, u32 base_lo, u32 base_hi, u32 size_lo, u32 size_hi, unsigned long type);
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void set_var_mtrr(
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unsigned long reg, unsigned long base, unsigned long size, unsigned long type);
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/**
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* Generic CPUID function.
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*
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@ -201,6 +209,48 @@ static inline __attribute__((always_inline)) void hlt(void)
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__asm__ __volatile__("hlt" : : : "memory");
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}
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/**
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* Optimized generic x86 assembly for clearing memory
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* @param addr address
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* @param size Size in bytes to clear
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*/
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static inline void clear_memory(void *addr, unsigned long size)
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{
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asm volatile(
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"cld \n\t"
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"rep; stosl\n\t"
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: /* No outputs */
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: "a" (0), "D" (addr), "c" (size>>2)
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);
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}
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/* in v2, these were specialized to the k8 for no apparent reason.
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* Also, clear_init_ram was set to noinline,
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* for reasons I do not understand (but may be important; see the comment */
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/* by yhlu 6.2005 */
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/* be warned, this file will be used core 0/node 0 only */
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//static void __attribute__((noinline)) clear_init_ram(void)
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static inline void clear_init_ram(void)
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{
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// ???
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// gcc 3.4.5 will inline the copy_and_run and clear_init_ram in post_cache_as_ram
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// will reuse %edi as 0 from clear_memory for copy_and_run part, actually it is increased already
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// so noline clear_init_ram
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// ???
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clear_memory(0, ((CONFIG_CBMEMK<<10) - CONFIG_CARSIZE));
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}
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/* be warned, this file will be used by core other than core 0/node 0 or core0/node0 when cpu_reset*/
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static void set_init_ram_access(void)
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{
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set_var_mtrr(0, 0x00000000, CONFIG_CBMEMK << 10, MTRR_TYPE_WRBACK);
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}
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void * bottom_of_stack(void);
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EXPORT_SYMBOL(bottom_of_stack);
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struct global_vars * global_vars(void);
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@ -260,4 +310,5 @@ EXPORT_SYMBOL(setup_resource_map_x_offset);
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void setup_resource_map(const struct rmap *rm, u32 max);
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EXPORT_SYMBOL(setup_resource_map);
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#endif /* ARCH_X86_CPU_H */
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@ -1,6 +1,7 @@
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#include <types.h>
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#include <cpu.h>
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#include <console.h>
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#include <globalvars.h>
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#include <uart8250.h>
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#include <stdarg.h>
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#include <string.h>
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@ -120,7 +120,8 @@ int find_file(const struct mem_file *archive, const char *filename, struct mem_f
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header = (struct lar_header *)walk;
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fullname = walk + sizeof(struct lar_header);
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printk(BIOS_SPEW, "LAR: seen member %s\n", fullname);
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printk(BIOS_SPEW, "LAR: %s@%p, size %d\n", fullname,
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header, ntohl(header->len));
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// FIXME: check checksum
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if (strcmp(fullname, filename) == 0) {
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@ -33,7 +33,9 @@ STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \
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INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
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$(src)/northbridge/amd/k8/raminit.c \
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$(src)/northbridge/amd/k8/dqs.c \
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$(src)/northbridge/amd/k8/reset_test.c \
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$(src)/arch/x86/pci_ops_conf1.c \
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$(src)/arch/x86/stage1_mtrr.c \
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$(src)/southbridge/amd/amd8111/stage1_smbus.c \
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$(src)/arch/x86/amd/model_fxx/init_cpus.c \
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$(src)/arch/x86/amd/model_fxx/dualcore.c \
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@ -22,6 +22,7 @@
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#define _MAINOBJECT
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#include <mainboard.h>
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#include <config.h>
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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|
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@ -33,7 +33,6 @@
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#define SB_HT_CHAIN_UNITID_OFFSET_ONLY 1
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#define ENABLE_APIC_EXT_ID 0
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#define LIFT_BSP_APIC_ID 1
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#warning clean up confusion on FIDVID. v2 was inconsistent.
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/* In v2 there is confusion on the settings of these.
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* The serengeti config sets it to zero.
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@ -44,3 +43,7 @@
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/* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores,
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* so may don't need to do twice */
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#define K8_SET_FIDVID_CORE0_ONLY 1
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/* architecture stuff which ought to be set "somewhere" "SOMEHOW" */
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/* preferably by asking the CPU, not be a DEFINE! */
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#define CPU_ADDR_BITS 40
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|
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@ -2972,3 +2972,40 @@ void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const u16 *sp
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}
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}
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}
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/**
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* initialize sdram. There was a "generic" function in v2 that was not really that useful.
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* we break it out by northbridge now to accomodate the different peculiarities of
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* different chipsets.
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*@param controllers Number of controllers
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*@param ctlr array of memory controllers
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*@param sysinfo pointer to sysinfo struct.
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*/
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void sdram_initialize(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo)
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{
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int i;
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/* Set the registers we can set once to reasonable values */
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for(i = 0; i < controllers; i++) {
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printk(BIOS_DEBUG, "Ram1.%d, ",i);
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sdram_set_registers(ctrl + i , sysinfo);
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}
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/* Now setup those things we can auto detect */
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for(i = 0; i < controllers; i++) {
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printk(BIOS_DEBUG, "Ram2.%d, ",i);
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sdram_set_spd_registers(ctrl + i , sysinfo);
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}
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/* Now that everything is setup enable the SDRAM.
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* Some chipsets do the work for us while on others
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* we need to it by hand.
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*/
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printk(BIOS_DEBUG, "Ram3\n");
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sdram_enable(controllers, ctrl, sysinfo);
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|
||||
printk(BIOS_DEBUG, "Ram4\n");
|
||||
|
||||
}
|
||||
|
|
|
|||
126
northbridge/amd/k8/reset_test.c
Normal file
126
northbridge/amd/k8/reset_test.c
Normal file
|
|
@ -0,0 +1,126 @@
|
|||
/*
|
||||
* K8 northbridge
|
||||
* This file is part of the coreboot project.
|
||||
* Copyright (C) 2004-2005 Linux Networx
|
||||
* (Written by Eric Biederman <ebiederman@lnxi.com> and Jason Schildt for Linux Networx)
|
||||
* Copyright (C) 2005-7 YingHai Lu
|
||||
* Copyright (C) 2005 Ollie Lo
|
||||
* Copyright (C) 2005-2007 Stefan Reinauer <stepan@openbios.org>
|
||||
* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
|
||||
*/
|
||||
/* This should be done by Eric
|
||||
2004.12 yhlu add dual core support
|
||||
2005.01 yhlu add support move apic before pci_domain in MB Config.lb
|
||||
2005.02 yhlu add e0 memory hole support
|
||||
2005.11 yhlu add put sb ht chain on bus 0
|
||||
*/
|
||||
|
||||
#include <mainboard.h>
|
||||
#include <console.h>
|
||||
#include <lib.h>
|
||||
#include <string.h>
|
||||
#include <mtrr.h>
|
||||
#include <macros.h>
|
||||
#include <spd.h>
|
||||
#include <cpu.h>
|
||||
#include <msr.h>
|
||||
#include <amd/k8/k8.h>
|
||||
#include <amd/k8/sysconf.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/hypertransport_def.h>
|
||||
#include <device/hypertransport.h>
|
||||
#include <mc146818rtc.h>
|
||||
#include <lib.h>
|
||||
#include <lapic.h>
|
||||
|
||||
int cpu_init_detected(unsigned nodeid)
|
||||
{
|
||||
unsigned long htic;
|
||||
u32 dev;
|
||||
|
||||
dev = PCI_BDF(0, 0x18 + nodeid, 0);
|
||||
htic = pci_conf1_read_config32(dev, HT_INIT_CONTROL);
|
||||
|
||||
return !!(htic & HTIC_INIT_Detect);
|
||||
}
|
||||
|
||||
int bios_reset_detected(void)
|
||||
{
|
||||
unsigned long htic;
|
||||
htic = pci_conf1_read_config32(PCI_BDF(0, 0x18, 0), HT_INIT_CONTROL);
|
||||
|
||||
return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect);
|
||||
}
|
||||
|
||||
int cold_reset_detected(void)
|
||||
{
|
||||
unsigned long htic;
|
||||
htic = pci_conf1_read_config32(PCI_BDF(0, 0x18, 0), HT_INIT_CONTROL);
|
||||
|
||||
return !(htic & HTIC_ColdR_Detect);
|
||||
}
|
||||
|
||||
void distinguish_cpu_resets(unsigned nodeid)
|
||||
{
|
||||
u32 htic;
|
||||
u32 device;
|
||||
device = PCI_BDF(0, 0x18 + nodeid, 0);
|
||||
htic = pci_conf1_read_config32(device, HT_INIT_CONTROL);
|
||||
htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect;
|
||||
pci_conf1_write_config32(device, HT_INIT_CONTROL, htic);
|
||||
}
|
||||
|
||||
void set_bios_reset(void)
|
||||
{
|
||||
unsigned long htic;
|
||||
htic = pci_conf1_read_config32(PCI_BDF(0, 0x18, 0), HT_INIT_CONTROL);
|
||||
htic &= ~HTIC_BIOSR_Detect;
|
||||
pci_conf1_write_config32(PCI_BDF(0, 0x18, 0), HT_INIT_CONTROL, htic);
|
||||
}
|
||||
|
||||
unsigned node_link_to_bus(unsigned node, unsigned link)
|
||||
{
|
||||
unsigned reg;
|
||||
|
||||
for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
|
||||
unsigned config_map;
|
||||
config_map = pci_conf1_read_config32(PCI_BDF(0, 0x18, 1), reg);
|
||||
if ((config_map & 3) != 3) {
|
||||
continue;
|
||||
}
|
||||
if ((((config_map >> 4) & 7) == node) &&
|
||||
(((config_map >> 8) & 3) == link))
|
||||
{
|
||||
return (config_map >> 16) & 0xff;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned get_sblk(void)
|
||||
{
|
||||
u32 reg;
|
||||
/* read PCI_BDF(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
|
||||
reg = pci_conf1_read_config32(PCI_BDF(0, 0x18, 0), 0x64);
|
||||
return ((reg>>8) & 3) ;
|
||||
}
|
||||
|
||||
unsigned get_sbbusn(unsigned sblk)
|
||||
{
|
||||
return node_link_to_bus(0, sblk);
|
||||
}
|
||||
|
||||
|
||||
Loading…
Add table
Add a link
Reference in a new issue