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This gets us back to a compiling k8 target.

Browse source 
This code has been tested on dbe62, and builds for qemu as well. 

the next step is testing on simnow. 

k8.h: add more prototypes and some required inline functions. 
cpu.h: same
serengeti: expand defines in mainboard.h, though we need a better 
mechanism; continue to fix initram.c, add new support files to Makefile
lib/console.c: include globalvars.h
lib/lar.c: Provide more informative print as the lar is scanned.
k8 north: needed reset_test.c from v2, fixes to raminit.c
arch/x86
Kconfig: new CONFIG variable CBMEMK, meaning coreboot mem k, memory
	used for coreboot. 
init_cpus.c: functions to start up CPUs
stage1_mtrr.c: bring over early mtrr support from v2.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@847 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich 2008-08-30 03:35:40 +00:00
commit ff2ddcb313
12 changed files with 450 additions and 3 deletions
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70
include/arch/x86/amd/k8/k8.h
View file

@ -690,6 +690,76 @@ void set_apicid_cpuid_lo(void);
void enable_fid_change(void);
void init_fidvid_bsp(unsigned bsp_apicid);
/* k8/northbridge.c */
void sdram_initialize(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo);
/* k8/reset_test.c */
void distinguish_cpu_resets(unsigned nodeid);
/* These are functions that MUST be inlined as we can not use a stack -- CAR or real ram */
/* by yhlu 6.2005 */
/* be warned, this file will be used other cores and core 0 / node 0 */
static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
{
__asm__ volatile (
/* We don't need cache as ram for now on */
/* disable cache */
"movl %cr0, %eax\n\t"
"orl $(0x1<<30),%eax\n\t"
"movl %eax, %cr0\n\t"
/* clear sth */
"movl $0x269, %ecx\n\t" /* fix4k_c8000*/
"xorl %edx, %edx\n\t"
"xorl %eax, %eax\n\t"
"wrmsr\n\t"
#if CONFIG_CARSIZE > 0x8000
"movl $0x268, %ecx\n\t" /* fix4k_c0000*/
"wrmsr\n\t"
#endif
/* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/
"movl $0xC0010010, %ecx\n\t"
// "movl $SYSCFG_MSR, %ecx\n\t"
"rdmsr\n\t"
"andl $(~(3<<18)), %eax\n\t"
// "andl $(~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn)), %eax\n\t"
"wrmsr\n\t"
/* Set the default memory type and disable fixed and enable variable MTRRs */
"movl $0x2ff, %ecx\n\t"
// "movl $MTRRdefType_MSR, %ecx\n\t"
"xorl %edx, %edx\n\t"
/* Enable Variable and Disable Fixed MTRRs */
"movl $0x00000800, %eax\n\t"
"wrmsr\n\t"
/* enable cache */
"movl %cr0, %eax\n\t"
"andl $0x9fffffff,%eax\n\t"
"movl %eax, %cr0\n\t"
);
}
static void disable_cache_as_ram_bsp(void)
{
__asm__ volatile (
// "pushl %eax\n\t"
"pushl %edx\n\t"
"pushl %ecx\n\t"
);
disable_cache_as_ram();
__asm__ volatile (
"popl %ecx\n\t"
"popl %edx\n\t"
// "popl %eax\n\t"
);
}
#endif /* ! ASSEMBLY */
#endif /* AMD_K8_H */

53
include/arch/x86/cpu.h
View file

@ -21,10 +21,11 @@
#ifndef ARCH_X86_CPU_H
#define ARCH_X86_CPU_H
#include <config.h>
#include <types.h>
#include <device/device.h>
#include <shared.h>
#include <mtrr.h>
#define X86_VENDOR_INTEL 0
#define X86_VENDOR_CYRIX 1
@ -81,6 +82,13 @@ struct cpuinfo_x86 {
u8 x86_mask;
};
/* prototypes for functions that may or may not be compiled in depending on cpu type */
void set_var_mtrr_x(
unsigned long reg, u32 base_lo, u32 base_hi, u32 size_lo, u32 size_hi, unsigned long type);
void set_var_mtrr(
unsigned long reg, unsigned long base, unsigned long size, unsigned long type);
/**
* Generic CPUID function.
*
@ -201,6 +209,48 @@ static inline __attribute__((always_inline)) void hlt(void)
__asm__ __volatile__("hlt" : : : "memory");
}
/**
* Optimized generic x86 assembly for clearing memory
* @param addr address
* @param size Size in bytes to clear
*/
static inline void clear_memory(void *addr, unsigned long size)
{
asm volatile(
"cld \n\t"
"rep; stosl\n\t"
: /* No outputs */
: "a" (0), "D" (addr), "c" (size>>2)
);
}
/* in v2, these were specialized to the k8 for no apparent reason.
* Also, clear_init_ram was set to noinline,
* for reasons I do not understand (but may be important; see the comment */
/* by yhlu 6.2005 */
/* be warned, this file will be used core 0/node 0 only */
//static void __attribute__((noinline)) clear_init_ram(void)
static inline void clear_init_ram(void)
{
// ???
// gcc 3.4.5 will inline the copy_and_run and clear_init_ram in post_cache_as_ram
// will reuse %edi as 0 from clear_memory for copy_and_run part, actually it is increased already
// so noline clear_init_ram
// ???
clear_memory(0, ((CONFIG_CBMEMK<<10) - CONFIG_CARSIZE));
}
/* be warned, this file will be used by core other than core 0/node 0 or core0/node0 when cpu_reset*/
static void set_init_ram_access(void)
{
set_var_mtrr(0, 0x00000000, CONFIG_CBMEMK << 10, MTRR_TYPE_WRBACK);
}
void * bottom_of_stack(void);
EXPORT_SYMBOL(bottom_of_stack);
struct global_vars * global_vars(void);
@ -260,4 +310,5 @@ EXPORT_SYMBOL(setup_resource_map_x_offset);
void setup_resource_map(const struct rmap *rm, u32 max);
EXPORT_SYMBOL(setup_resource_map);
#endif /* ARCH_X86_CPU_H */