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The m57sli almost builds. It's pretty empty. The dtc is not run .

Browse source 
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Marc Jones <marc.jones@amd.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@702 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich 2008-08-01 17:03:22 +00:00
commit 06ced7c09a
13 changed files with 804 additions and 1 deletions
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56
include/arch/x86/amd_k8.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ROM_CODE_SEG 0x08
#define ROM_DATA_SEG 0x10
#define CACHE_RAM_CODE_SEG 0x18
#define CACHE_RAM_DATA_SEG 0x20
#define IORR_FIRST 0xC0010016
#define IORR_LAST 0xC0010019
#define MTRR_READ_MEM (1 << 4)
#define MTRR_WRITE_MEM (1 << 3)
#define SYSCFG_MSR 0xC0010010
#define SYSCFG_MSR_TOM2En (1 << 21)
#define SYSCFG_MSR_MtrrVarDramEn (1 << 20)
#define SYSCFG_MSR_MtrrFixDramModEn (1 << 19)
#define SYSCFG_MSR_MtrrFixDramEn (1 << 18)
#define SYSCFG_MSR_UcLockEn (1 << 17)
#define SYSCFG_MSR_ChxToDirtyDis (1 << 16)
#define SYSCFG_MSR_ClVicBlkEn (1 << 11)
#define SYSCFG_MSR_SetDirtyEnO (1 << 10)
#define SYSCFG_MSR_SetDirtyEnS (1 << 9)
#define SYSCFG_MSR_SetDirtyEnE (1 << 8)
#define SYSCFG_MSR_SysVicLimitMask ((1 << 8) - (1 << 5))
#define SYSCFG_MSR_SysAckLimitMask ((1 << 5) - (1 << 0))
#define IORR0_BASE 0xC0010016
#define IORR0_MASK 0xC0010017
#define IORR1_BASE 0xC0010018
#define IORR1_MASK 0xC0010019
#define TOP_MEM 0xC001001A
#define TOP_MEM2 0xC001001D
#define TOP_MEM_MASK 0x007fffff
#define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10)

41
include/arch/x86/mtrr.h Normal file
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#ifndef ARCH_X86_MTRR_H
#define ARCH_X86_MTRR_H
/* These are the region types */
#define MTRR_TYPE_UNCACHEABLE 0
#define MTRR_TYPE_WRCOMB 1
/*#define MTRR_TYPE_ 2*/
/*#define MTRR_TYPE_ 3*/
#define MTRR_TYPE_WRTHROUGH 4
#define MTRR_TYPE_WRPROT 5
#define MTRR_TYPE_WRBACK 6
#define MTRR_NUM_TYPES 7
#define MTRRcap_MSR 0x0fe
#define MTRRdefType_MSR 0x2ff
#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
#define NUM_FIXED_RANGES 88
#define MTRRfix64K_00000_MSR 0x250
#define MTRRfix16K_80000_MSR 0x258
#define MTRRfix16K_A0000_MSR 0x259
#define MTRRfix4K_C0000_MSR 0x268
#define MTRRfix4K_C8000_MSR 0x269
#define MTRRfix4K_D0000_MSR 0x26a
#define MTRRfix4K_D8000_MSR 0x26b
#define MTRRfix4K_E0000_MSR 0x26c
#define MTRRfix4K_E8000_MSR 0x26d
#define MTRRfix4K_F0000_MSR 0x26e
#define MTRRfix4K_F8000_MSR 0x26f
#if !defined (ASSEMBLY)
void x86_setup_var_mtrrs(unsigned address_bits);
void x86_setup_mtrrs(unsigned address_bits);
int x86_mtrr_check(void);
#endif
#endif /* ARCH_X86_MTRR_H */