This patch adds some simple constants to more easily write and do math
with frequencies, analogous to the existing KiB, MiB and GiB constants
for sizes. They are exemplary added to the Veyron_Pinky/Rk3288 code for
now and will hopefully be adopted by other parts of the codebase in the
future.
BUG=None
TEST=Compiled Veyron_Pinky.
Change-Id: I4a1927fd423eb96d3f76f7e44b451192038b02e0
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221800
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Provide a weak implemenation of usb_setup_utmip function for those stages that
do not include usb.c.
BUG=chrome-os-partner:32684
BRANCH=None
TEST=Compiles successfully
Change-Id: Ib235cf039a17204ef7e06d545a3c86b75aff5b4c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/221575
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
This function needs to be available in different LOGLEVELs.
BUG=chrome-os-partner:28234
BRANCH=samus
TEST=USE=quiet-cb emerge-samus coreboot
Change-Id: Ia8f0d05af24c9070c8c9241a3a7e137f845d1cab
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221540
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
A higher drive setting is used for fast link training, once the
link training succeeds, a known-good drive setting will be used
for the main stream transactions.
For full link training sequence, the sink devices may ask for a
preferred drive setting, thus this drive setting should be used
for the main stream transactions too.
BUG=chrome-os-partner:32129
TEST=all panels on blaze/big devices work fine.
Change-Id: Icc540650dc1329af07fd9ee4661eb7fad435fde4
Signed-off-by: Neil Chen <neilc@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/219544
Reviewed-by: Julius Werner <jwerner@chromium.org>
The original dp driver supports only fast link training and a
special drive setting is used for the link training sequence.
This might not be accepted by all panels. The better way is to
go through full link training sequence to negotiate for a best
drive setting.
With the change, dp driver will try fast link training first,
this is same as before. If it fails in fast link training, will
try full link training.
BUG=chrome-os-partner:32129
TEST=all panels on blaze/big devices work fine.
Change-Id: I6f3402c4c5993a156c965c7f52b011d336a2946f
Signed-off-by: Neil Chen <neilc@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/219543
Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
rockchip_spi_slave has a fifo_size member which doesn't change.
This just replaces the struct member with a #define.
BUG=none
BRANCH=none
TEST=built and booted on Pinky
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I9ea5cdad49ee10c5f32304d0909c4a7e74a261f9
Reviewed-on: https://chromium-review.googlesource.com/220471
Reviewed-by: Julius Werner <jwerner@chromium.org>
This re-factors rockchip_spi to remove speed_hz which will instead be
passed in via rockchip_spi_init(), thus making it easier to support
other boards which may have different slave devices attached.
BUG=none
BRANCH=none
TEST=built and booted on Pinky
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I7baf0fa0a2660e3c975847fdec3eb92bcd0d6c10
Reviewed-on: https://chromium-review.googlesource.com/220411
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch moves init for I2C, SPI, ChromeOS GPIOs to the
board-specific bootblock init function on Pinky, the idea being
to isolate SoC code so that it's more readily adaptable for
different boards.
BUG=none
BRANCH=none
TEST=built and booted on Pinky
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I75516bbd332915c1f61249844e18415b4e23c520
Reviewed-on: https://chromium-review.googlesource.com/220410
Reviewed-by: Julius Werner <jwerner@chromium.org>
Since the UART which is used for the serial console may change from
board-to-board, this moves CONSOLE_SERIAL_UART_ADDRESS from rk3288's
Kconfig into Pinky's Kconfig.
BUG=none
BRANCH=none
TEST=built and booted on pinky
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I29837a72d8cf205a144494a6c8ce350465118b34
Reviewed-on: https://chromium-review.googlesource.com/221438
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch creates a new mechanism to define the static memory layout
(primarily in SRAM) for a given board, superseding the brittle mass of
Kconfigs that we were using before. The core part is a memlayout.ld file
in the mainboard directory (although boards are expected to just include
the SoC default in most cases), which is the primary linker script for
all stages (though not rmodules for now). It uses preprocessor macros
from <memlayout.h> to form a different valid linker script for all
stages while looking like a declarative, boilerplate-free map of memory
addresses to the programmer. Linker asserts will automatically guarantee
that the defined regions cannot overlap. Stages are defined with a
maximum size that will be enforced by the linker. The file serves to
both define and document the memory layout, so that the documentation
cannot go missing or out of date.
The mechanism is implemented for all boards in the ARM, ARM64 and MIPS
architectures, and should be extended onto all systems using SRAM in the
future. The CAR/XIP environment on x86 has very different requirements
and the layout is generally not as static, so it will stay like it is
and be unaffected by this patch (save for aligning some symbol names for
consistency and sharing the new common ramstage linker script include).
BUG=None
TEST=Booted normally and in recovery mode, checked suspend/resume and
the CBMEM console on Falco, Blaze (both normal and vboot2), Pinky and
Pit. Compiled Ryu, Storm and Urara, manually compared the disassemblies
with ToT and looked for red flags.
Change-Id: I005506add4e8fcdb74db6d5e6cb2d4cb1bd3cda5
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213370
BUG=chrome-os-partner:31424,chromeos-os-partner:32380
TEST=Build a BIOS image and check the value is applied correctly.
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Change-Id: I0adda3643776b259a635a021babd983090f1df43
Reviewed-on: https://chromium-review.googlesource.com/220475
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Need END tag, "REG_SCRIPT_END", to indicate the end of smbus_init_script.
BUG=chromium:416651
TEST=test on Auron.
Change-Id: I1f5624f4c6ce7f0e8ceb8971aaa595d99e9ff82e
Signed-off-by: Ryan Lin <ryan.lin@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/220934
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Kenji Chen <kenji.chen@intel.com>
BUG=chrome-os-partner:31424
BRANCH=none
TEST=build only, due to I don't have broadwell system with wifi to test
need somebody help me to verify
Change-Id: I52360176e135ea7f01cc67a926be4870265f57d1
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/220743
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This patch adds the macros __ROMSTAGE__ and __RAMSTAGE__ which get
predefined in their respective stages by make, so that we have one
specific macro for every stage. It also renames __BOOT_BLOCK__ and
__VER_STAGE__ to __BOOTBLOCK__ and __VERSTAGE__ for consistency.
This change is intended to provided finer control and clearer
communication of intent after we added a new (optional) stage that falls
under __PRE_RAM__, and will hopefully provide some robustness for the
future (we don't want to end up always checking for romstage with #if
defined(__PRE_RAM__) && !defined(__BOOT_BLOCK__) &&
!defined(__VER_STAGE__) && !defined(__YET_ANOTHER_PRERAM_STAGE__)). The
__PRE_RAM__ macro stays as it is since many features do in fact need to
differentiate on whether RAM is available. (Some also depend on whether
RAM is available at the end of a stage, in which case #if
!defined(__PRE_RAM__) || defined(__ROMSTAGE__) should now be
authoritative.)
It's unfeasable to change all existing occurences of __PRE_RAM__ that
would be better described with __ROMSTAGE__, so this patch only
demonstratively changes a few obvious ones in core code.
BUG=None
TEST=None (tested together with dependent patch).
Change-Id: I6a1f25f7077328a8b5201a79b18fc4c2e22d0b06
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219172
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Disable ADSP D3 and SRAM power gating features by default, and make
the devicetree.cb flags into enable flags instead of disable.
BUG=chrome-os-partner:31588
BRANCH=samus,auron
TEST=build and boot on samus
Change-Id: Ib881290acc07819b55d776d4696bf0062df4d50e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220863
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
BUG=None
TEST=Boot Veyron Pinky and measure i2c clock frequency
Change-Id: I04d9fa75a05280885f083a828f78cf55811ca97d
Signed-off-by: huang lin <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/219660
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Julius Werner <jwerner@chromium.org>
BUG=None
TEST=Boot Veyron Pinky and test the VDD_LOG
Change-Id: Ie2eef918e04ba0e13879e915b0b0bef44aef550e
Signed-off-by: huang lin <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/219753
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Julius Werner <jwerner@chromium.org>
Add ddr3-samsung-2GB config and modify 533mhz linit.
Support ddr3 freq up to 800mhz.
Enable ODT at LPDDR3.
BUG=None
TEST=Boot Veyron Pinky
Change-Id: Ic02a381985796a00644c5c681b96f10ad1558936
Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/220113
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: Lin Huang <hl@rock-chips.com>
Commit-Queue: Julius Werner <jwerner@chromium.org>
This patch adds support for the board changes in rev2 (board_id = 0001).
It also moves the existing mainboard.c code around a bit to group it by
component.
BUG=chrome-os-partner:32139
TEST=Booted on rev1. Confirmed SD card still works. Confirmed power
button was still as broken as before.
Change-Id: Ifc4876687db64ca50e41d009d911446129d57b1b
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220251
The static gpio_t initializers are stylish, but they are still a little
too annoying to write and read in day-to-day use. Let's wrap that in a
macro to make it a little easier to handle.
BUG=None
TEST=None
Change-Id: I385ae5182776c8cbb20bbf3c79b986628040f1cf
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220250
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This updates timer.h to #include the header necessary for u32,
and to change the one instance of uint32_t to u32 to be uniform.
BUG=none
BRANCH=none
TEST=compiled
Change-Id: Ie406fb1f518af5d1fd1e623630b2bcbbef35622c
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220612
Reviewed-by: Julius Werner <jwerner@chromium.org>
The Serial Peripheral Flash Interface (SPFI) block allows
communication with various devices over the SPI bus.
It uses a configurable transaction interface and it clocks
the bus according to the configured command, address, gap (aka
dummy) and data lengths.
This controller requires the SPI_ATOMIC_SEQUENCING flag set
(write and read done in the same transaction) as it cannot
directly control CS and will assert/de-assert CS at the
beginning/end of a transaction itself.
Note that the size of any transfer cannot be greater than
64KB - 1, as this is configured in a 16-bit field.
The SOC has 2 SPFI interfaces each of them providing 5 slave select
lines. SPFI 0 supports single and dual modes, SPFI 1 supports
single, dual and quad modes.
For SPFI interface 0:
- The block needs the system PLL and the following top level
SPI clock registers to be set:
- CR_cr_top_spi0clkinternal_CTRL[2:0] with division value
- CR_MIPS_CLOCK_GATE[19]: bit cr_top_SPI0CLKOUT_MIPS set
- CR_cr_top_SPI0CLKOUT_CTRL[6:0] with division value
- The following MFIO configuration paramters are also required:
Signal name Pad name MFIO mode
spim0_d0_txd MFIO_MIPS_10 0
spim0_d1_rxd MFIO_MIPS_9 0
spim0_mclk MFIO_MIPS_8 0
spim0_cs0 MFIO_MIPS_2 1
spim0_cs1 MFIO_MIPS_1 1
spim0_cs2 MFIO_MIPS_55 1
MFIO_MIPS_28 1
spim0_cs3 MFIO_MIPS_56 1
MFIO_MIPS_29 1
spim0_cs4 MFIO_MIPS_57 1
MFIO_MIMPS_30 1
For SPFI interface 1:
- The block needs the system PLL and the following top level
SPI clock registers to be set:
- CR_cr_top_spi1clkinternal_CTRL[2:0] with division value
- CR_MIPS_CLOCK_GATE[20]: bit cr_top_SPI1CLKOUT_MIPS set
- CR_cr_top_SPI1CLKOUT_CTRL[6:0] with division value
- The following MFIO configuration paramters are also required:
Signal name Pad name MFIO mode
spim1_d0_txd MFIO_MIPS_5 0
spim1_d1_rxd MFIO_MIPS_4 0
spim1_mclk MFIO_MIPS_3 0
spim1_d2 MFIO_MIPS_6 0
spim1_d3 MFIO_MIPS_7 0
spim1_cs0 MFIO_MIPS_0 0
spim1_cs1 MFIO_MIPS_1 0
MFIO_MIPS_58 1
spim1_cs2 MFIO_MIPS_2 0
MFIO_MIPS_55 2
MFIO_MIPS_31 1
spim1_cs3 MFIO_MIPS_56 2
spim1_cs4 MFIO_MIPS_57 2
BUG=chrome-os-partner:31438, chrome-os-partner:32441
TEST=Tested as bare-metal driver on Pistachio FPGA
Change-Id: Ib257eb6236bd2895281175871b4ab979660f1239
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://chromium-review.googlesource.com/217320
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Danube has become Pistachio, let's rename all instances where this SOC
is mentioned.
BUG=none
TEST=board urara still builds
Change-Id: Ie5ede401c4f69ed5d832a9eabac008eeac6db62d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220401
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Actual timer support is not yet available for Danube, it will be added
soon. For now, just to make the target build, modify it to use
GENERIC_UDELAY and HAVE_MONOTONIC_TIMER configuration option.
BUG=none
TEST=the target builds again
Change-Id: Ie3289eace9d2baadd01bd641b5dffc635ac80c0f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220395
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In order to report the GPE that woke the system to the kernel
coreboot needs to keep track of the first GPE wake source and
save it in NVS so it can be returned in \_GPE._SWS method.
This is similar to the saving of PM1 status but needs to go
through all the GPE0_STS registers and check for enabled and
triggered events.
A bit of cleanup is done for areas that were touched:
- ramstage.c:s3_resume_prepare() was not indented with tabs
- platform.asl was not formatted correctly
BUG=chrome-os-partner:8127
BRANCH=samus,auron
TEST=manual:
- suspend/resume and wake from EC event like keyboard:
ACPI _SWS is PM1 Index -1 GPE Index 112 ("special" GPIO27)
- suspend/resume and wake from RTC event:
ACPI _SWS is PM1 Index 10 GPE Index -1 (RTC)
- suspend/resume and wake from power button:
ACPI _SWS is PM1 Index 8 GPE Index -1
- suspend/resume and wake from touchpad:
ACPI _SWS is PM1 Index -1 GPE Index 13
- suspend/resume and wake from WLAN:
ACPI _SWS is PM1 Index -1 GPE Index 10
Change-Id: I9bfbbe4385f2acc2a50f41ae321b4bae262b7078
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220324
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add event log entry if GPIO27 is used to wake the system.
This GPIO is treated separately from other GPE and it is
one of the only events that can wake from Deep Sx.
BUG=chrome-os-partner:31549
BRANCH=samus
TEST=samus: suspend/resume and wake from keypress, check for
GPIO27 event in event log.
Change-Id: I38a44a62f68288a4ae3f97fe078ca222fd01390a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220323
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add GENERIC_UDELAY Kconfig option so that a generic
udelay() implementation is provided utilizing the
monotonic timer. That way each board/chipset doesn't
need to duplicate the same udelay(). Additionally,
assume that GENERIC_UDELAY implies init_timer()
is not required.
BUG=None
BRANCH=None
TEST=Built nyan, ryu, and rambi. May need help testing.
Change-Id: Idd26de19eefc91ee3b0ceddfb1bc2152e19fd8ab
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219719
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Instead of open coding monotonic timer usage,
use the stopwatch API.
BUG=None
BRANCH=None
TEST=None
Change-Id: Ia63a05850a1b6afdc42c2422332f77af516d27e3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219716
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Instead of using rela_time use the stopwatch API as the
semantics fit perfectly with the expiration usage.
BUG=None
BRANCH=None
TEST=None, but similar usage tested on tegra132.
Change-Id: Iff3293debc2f85553c9e9b765084e5c00720012c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219713
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Instead of using rela_time use the stopwatch API as the
semantics fit perfectly with the expiration usage.
BUG=None
BRANCH=None
TEST=Built, but similar usage tested on tegra132.
Change-Id: I6d3f3da4e035e872890d8b67947b17a981673dba
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219712
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Simplify the timed operations by using the stopwatch API.
BUG=None
BRANCH=None
TEST=Built and booted to kernel. Analyzed logs. Output as expected.
Change-Id: Iffc32fcb9b8bfdcfbef67f563ac3014912f82e7f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219494
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Most Baytrail based devices MMIO registers are reported in ACPI
space and the device's PCI config space is disabled. The PCI config
space is required for many "legacy" OSs that don't have the ACPI
driver loading mechanism. Depthcharge signals the legacy boot
path via the SMI 0xCC and the coreboot SMI handler can switch the
device specific registers to re-enable PCI config space.
BUG=chrome-os-partner:30836
BRANCH=None
TEST=Build and boot Rambi SeaBIOS.
Change-Id: Ia5e54f4330eda10a01ce3de5aa4d86779d6e1bf9
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: https://chromium-review.googlesource.com/219801
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Mike Loptien <mike.loptien@se-eng.com>
Tested-by: Mike Loptien <mike.loptien@se-eng.com>
OBFF: Disable it by clear bit fields in that W/O register.
RO: Enable Relaxed Ordering from each enabled Root Port.
Linker Arbiter: Set it to recommeded setting.
BUG=None
TEST=Build a image and check the setting are applied correctly on
Samub.
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Change-Id: I284e9eba1c2fceb690d3ef48b45a6f36d07ff84c
Reviewed-on: https://chromium-review.googlesource.com/219993
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Kenji Chen <kenji.chen@intel.com>
Tested-by: Kenji Chen <kenji.chen@intel.com>
Extended PCIe Capability and Advanced Error Report locates at
offset 0x100 is W/O, and the subsequent write following the 1st
write to the register takes no effect.
BUG=chrome-os-partner:31424.
TEST=Build a image and check the programming value is correct on
Samus.
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Change-Id: I0bed30f516ee0307b4a86cad2f669a18ff4994db
Reviewed-on: https://chromium-review.googlesource.com/219985
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Configure IOSF Port and Grant Count.
BUG=None
TEST=Build coreoot image and run on Samus to confirm the setting
is properly applied.
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Change-Id: If387a23749b6e9470c7e67286234e18ab3e423b3
Reviewed-on: https://chromium-review.googlesource.com/219523
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
BUG=chrome-os-partner:32015
BRANCH=None
TEST=successfully suspend/resume on Rush/Ryu
Signed-off-by: Yen Lin <yelin@nvidia.com>
Change-Id: I11cca0a8f5e7a36c1fff690c8070c74706348949
Reviewed-on: https://chromium-review.googlesource.com/214580
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Yen Lin <yelin@nvidia.com>
Tested-by: Yen Lin <yelin@nvidia.com>
With VPD blob of certain format, CBFS cache on storm proves to be not
large enough. This patch makes it bigger, it is still well above the
area preserved for the NSS.
BUG=chrome-os-partner:32152
TEST=the system now boots with the VPD it used to fail booting.
Change-Id: Ia88b598ad5e4b6adcbd87d865e43be57fbf0ea98
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219572
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Cleanup of functions to write to clk_enb and rst_dev registers and addition of
clock_disable and clock_set_reset functions to provide a complete API for
updating the registers.
BUG=chrome-os-partner:31821
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt on ryu. Compiles
successfully on rush
Change-Id: Icb8081fe3d80174c920eaaecf5cbb0aa912d5b19
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/219191
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
BUG=None
TEST=Modify settings, build and update the image to Samus and
check the settings are applied to Registers.
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Change-Id: I3d407b8f1cb4a6ea3d6879a8581156a73f98220f
Reviewed-on: https://chromium-review.googlesource.com/219073
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Do the absolute minimum needed to allow the DPAUX mux ctl write
for I2C6. This leaves HOST1X off (reset and clock disabled) to
avoid a conflict with any kernel display driver init.
I2C6 init/enable will be moved to ramstage in the next CL.
BUG=chrome-os-partner:31820
BRANCH=none
TEST=Dumped Speaker Driver (AD SSM4567) regs on Ryu, looks good.
Change-Id: I0760222f1d7ccee207ae9871aeed3e2ddbca3dca
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/218900
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
this change syncs the i2c driver with the one in depthcharge.
BUG=None
TEST=Booted Veyron Pinky
BRANCH=None
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I0d0fdefa58c5b4cc5c991be40796a800ccf074a5
Reviewed-on: https://chromium-review.googlesource.com/218873
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Bootblock stack on Danube should be SRAM and defined separately from
the rest of the coreboot stack. The actual coreboot stack will be
defined later.
The top of the stack should be above the bottom, as the stack grows
towards lower addresses.
BUG=chrome-os-partner:31438
TEST=ran bootblock on simulator under codescape, observed stack
properly initialized.
Change-Id: I3c37c8b5a1c0e7fd19411558a8f6d899fc283191
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218732
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
