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Broadwell: Revise programming flow for write-once registers

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Extended PCIe Capability and Advanced Error Report locates at
offset 0x100 is W/O, and the subsequent write following the 1st
write to the register takes no effect.

BUG=chrome-os-partner:31424.
TEST=Build a image and check the programming value is correct on
Samus.
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Change-Id: I0bed30f516ee0307b4a86cad2f669a18ff4994db
Reviewed-on: https://chromium-review.googlesource.com/219985
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Kenji Chen 2014-09-25 21:34:42 +08:00 • committed by chrome-internal-fetch
commit d2862b6c1c
1 changed files with 3 additions and 4 deletions
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7
src/soc/intel/broadwell/pcie.c
View file

@ -547,16 +547,15 @@ static void pch_pcie_early(struct device *dev)
pcie_update_cfg8(dev, 0xf5, 0x0f, 0);
/* Set Extended Capability to offset 200h and Advanced Error Report. */
pcie_update_cfg(dev, 0x100, ~(1 << 29) & ~0xfffff, (1 << 29) | 0x10001);
if (rp == 1 || rp == 5 || rp == 6)
pcie_update_cfg8(dev, 0xf7, ~0xc, 0);
/* Set EOI forwarding disable. */
pcie_update_cfg(dev, 0xd4, ~0, (1 << 1));
/* Set something involving advanced error reporting. */
pcie_update_cfg(dev, 0x100, ~((1 << 20) - 1), 0x10001);
pcie_update_cfg(dev, 0x100, ~0, (1 << 29));
/* Read and write back write-once capability registers. */
pcie_update_cfg(dev, 0x34, ~0, 0);
pcie_update_cfg(dev, 0x40, ~0, 0);