erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Samus: Synchronization with FRC to enable PCIe Relaxed Order.

Browse source 
BUG=None
TEST=Modify settings, build and update the image to Samus and
check the settings are applied to Registers.
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Change-Id: I3d407b8f1cb4a6ea3d6879a8581156a73f98220f
Reviewed-on: https://chromium-review.googlesource.com/219073
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Kenji Chen 2014-09-20 01:39:20 +08:00 • committed by chrome-internal-fetch
commit 8455d95442
1 changed files with 3 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

3
src/soc/intel/broadwell/lpc.c
View file

@ -204,6 +204,9 @@ static const struct reg_script pch_misc_init_script[] = {
/* Clear status bits to prevent unexpected wake */
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x3310, 0x0000002f),
REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x3f02, ~0x0000000f, 0),
/* Enable PCIe Releaxed Order */
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2314, (1 << 31) | (1 << 7)),
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x1114, (1 << 15) | (1 << 14)),
/* Setup SERIRQ, enable continuous mode */
REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)),
#if !CONFIG_SERIRQ_CONTINUOUS_MODE