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344 commits

Author SHA1 Message Date
Li-Ta Lo
7997262b98 minor bug fix in chipset init code 2001-01-29 09:56:21 +00:00
Li-Ta Lo
ce8453cbde minor changes to to reflect 730 2001-01-29 08:01:49 +00:00
Li-Ta Lo
f23356e68f SiS 730 Works lsls 2001-01-29 07:58:42 +00:00
Li-Ta Lo
ffa86f1fb3 fixed a typo on 730 device id 2001-01-29 07:53:52 +00:00
Li-Ta Lo
70d361e5f8 fix some rounding problem 2001-01-29 02:12:35 +00:00
Ronald G. Minnich
e4a129a678 minor changes for via. 
You can build for vt5292A4 by:
cd romimages/RON_VIA_SPD
make

Note that we now use 2.4.0 release

multiple SDRAM do not work yet.
 2001-01-27 00:54:43 +00:00
Ronald G. Minnich
ef33ec89a4 superio.c 2001-01-19 17:10:45 +00:00
Ronald G. Minnich
ef2a712106 added files for 440bx 2001-01-19 17:02:36 +00:00
Li-Ta Lo
ba090cb1cc add 2.4.0 kernel patch, sisfb_lite works with XFree86 3.3.6 2001-01-19 14:53:13 +00:00
Ronald G. Minnich
31370304b1 Only enable CPU pipeline if option ENABLE_SIS630_CPU_PIPELINE is set 2001-01-19 00:11:45 +00:00
Ronald G. Minnich
b56912ec3a Fixes for CMD_LINE, and other fixes to set up ga-6bxc. 
mtrr.c, remove redundant define
string.h bug with 0 in strlen
 2001-01-18 23:11:26 +00:00
Ronald G. Minnich
c4de6e712f Sample file 2001-01-17 23:50:57 +00:00
Li-Ta Lo
75ac3d4d1a enable CPU pipeline and disable DRAM delay 2001-01-17 08:18:38 +00:00
Ronald G. Minnich
7d897e96f8 Lanner em-370 Config file and an example config 2001-01-16 22:51:37 +00:00
Ronald G. Minnich
ede94585e0 We now use memory size reported in VIA northbridge registers 2001-01-07 21:21:48 +00:00
Li-Ta Lo
719f89882d found an very very old bug on setting MTRR range 2001-01-04 07:50:56 +00:00
Li-Ta Lo
12c01a0f30 Fixed a fatal bug in framebuffer_on(), XFree86 3.3.6 O.K. 2000-12-27 02:49:33 +00:00
Li-Ta Lo
360a0c4242 replace Ron's test12 patch with my own one 2000-12-26 01:23:48 +00:00
Ronald G. Minnich
9693e9ba1a Support for test12 2000-12-22 22:29:06 +00:00
Li-Ta Lo
714d9a2049 add irq table for SiS 630S demo board 2000-12-22 07:15:39 +00:00
Li-Ta Lo
ce35c2f7b1 clean up for SiS630S 2000-12-22 02:42:55 +00:00
Li-Ta Lo
006c147a76 add option HAVE_PIRQ_TABLE 2000-12-21 00:59:09 +00:00
Li-Ta Lo
7c4b9e606a prepare for SiS 730 support, let's wait and see 2000-12-20 09:08:40 +00:00
Ronald G. Minnich
607661601a Support for getting keyboard, framebuffer working 2000-12-20 04:42:36 +00:00
Ronald G. Minnich
d920c24fa6 turn on refresh. 2000-12-19 05:52:35 +00:00
Ronald G. Minnich
b18b69befa missed setting refresh on! 2000-12-19 05:51:50 +00:00
Ronald G. Minnich
6a11a06df1 More stuff for via, including superio 2000-12-19 03:14:05 +00:00
Ronald G. Minnich
08cfcf6313 GAS bug (again) 2000-12-18 22:22:17 +00:00
Ronald G. Minnich
b38a6eec1c More chipset setup for ram. 2000-12-18 03:21:04 +00:00
Ronald G. Minnich
980dff7eff Continuing fixes for acer. 2000-12-15 00:58:14 +00:00
Ronald G. Minnich
bb8dc3b9b7 Put HACK back in for 2.2. kernels for IRQ routing. 2000-12-13 05:31:38 +00:00
Ronald G. Minnich
13275b3fea Fixes for various acer stuff. Also, you can now #ifdef out the real-mode stuff 
in start32.inc.
 2000-12-13 03:49:26 +00:00
Ronald G. Minnich
651393b2e0 add enable for flash write. We still need to know the device # of 
SB
 2000-12-11 05:41:00 +00:00
Li-Ta Lo
3283b9410a remove test6 patch, every body should use test11 patch instead 2000-12-11 05:08:00 +00:00
Ronald G. Minnich
a5a4445593 This might actually work! 2000-12-09 14:56:54 +00:00
Ronald G. Minnich
7fb6bba49f added DoC support 2000-12-09 03:52:16 +00:00
Ronald G. Minnich
81b6860bae fixes to ipl.S for acer 2000-12-08 22:58:04 +00:00
Ronald G. Minnich
82a6bdc293 vastly improved IPL and chipsizer. Looks like DoC is a go on this machine, but 
we'll see.
 2000-12-08 19:45:35 +00:00
Ronald G. Minnich
43597ab580 almost there. 2000-12-08 06:06:31 +00:00
Ronald G. Minnich
edbdd1c15d Simple ipl.S 2000-12-08 01:00:34 +00:00
Ronald G. Minnich
c50d44dd43 ipl for DoC for ASUS CUA 2000-12-08 00:43:59 +00:00
Li-Ta Lo
cd92ec8ef9 add LPT support 2000-12-07 07:34:40 +00:00
Li-Ta Lo
27a812455f fix some typo 2000-12-07 01:43:28 +00:00
Ronald G. Minnich
ff291c1f67 Closer to correct. 
Detects SPD correctly, but the bank stuff really looks wrong.
 2000-12-07 00:39:49 +00:00
Li-Ta Lo
54e665686e more clean up for printk messages 2000-12-06 11:02:36 +00:00
Li-Ta Lo
79ff9ed5cc MSR names for L2 cache init 2000-12-06 10:58:20 +00:00
Li-Ta Lo
75bdd79519 add option FINAL_MAINBOARD_FIXUP 2000-12-06 06:53:51 +00:00
Li-Ta Lo
f2ff30716e add Config file for Matsonic M/Bs 2000-12-06 06:52:58 +00:00
Li-Ta Lo
9b0e700d23 clean up and some document for serial init stuff 2000-12-06 06:44:07 +00:00
Li-Ta Lo
ba4403a177 finally, a fullproof implementation for MTRR setting 2000-12-06 03:58:57 +00:00