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coreboot/src
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Li-Ta Lo 79ff9ed5cc MSR names for L2 cache init
2000-12-06 10:58:20 +00:00
..
cpu finally, a fullproof implementation for MTRR setting 2000-12-06 03:58:57 +00:00
include MSR names for L2 cache init 2000-12-06 10:58:20 +00:00
kernel_patches added kernel patches to new src tree 2000-11-03 01:24:06 +00:00
lib a smarter Late MTRR implementation 2000-12-05 07:25:32 +00:00
mainboard add option FINAL_MAINBOARD_FIXUP 2000-12-06 06:53:51 +00:00
northbridge changes to intel which still don't fix SCSI 2000-12-05 00:40:55 +00:00
northsouthbridge/sis/630 add more specific information on M-Systems' AppNote 2000-12-04 06:46:37 +00:00
pc80 clean up and some document for serial init stuff 2000-12-06 06:44:07 +00:00
ram reorg 2000-10-17 03:24:23 +00:00
sdram fixes. 2000-11-17 17:02:45 +00:00
southbridge Setting up VIA VT5292 to see how it works. We've already hit a snag ... 2000-11-29 05:52:34 +00:00
superio clean up and some document for serial init stuff 2000-12-06 06:44:07 +00:00