vastly improved IPL and chipsizer. Looks like DoC is a go on this machine, but
we'll see.
This commit is contained in:
Ronald G. Minnich
parent
43597ab580
commit
82a6bdc293
2 changed files with 94 additions and 18 deletions
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@ -45,10 +45,19 @@ floppy: all
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# we need the vmlinux.bin.gz padded out and then cat the linuxbios.rom
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# at then end. We always copy it to /tmp so that a waiting root shell
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# can put it on the floppy (see ROOTDOIT)
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romimage: linuxbios.rom vmlinux.bin.gz.block
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romimage: linuxbios.rom vmlinux.bin.gz.block docipl
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cat vmlinux.bin.gz.block linuxbios.rom > romimage
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cp romimage /tmp
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docipl: ipl.o
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objcopy -O binary -R .note -R .comment -S ipl.o adocipl
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dd if=adocipl of=docipl bs=1 skip=1040384
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# I have noe idea why you can not use $(CPUFLAGS) to compile ipl.S
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# a bug with -Di686 ??
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ipl.o: $(TOP)/src/northbridge/acer/m1631/ipl.S
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gcc -save-temps -c -I$(TOP)/src/include -I$(TOP)/src $<
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linuxbios.rom: linuxbios.strip mkrom
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./mkrom -s 64 -f -o linuxbios.rom linuxbios.strip
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@ -1,3 +1,4 @@
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#include <asm.h>
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#include <cpu/p5/macros.h>
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#define DOC_WIN_SEG 0xfe00
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#define DOC_STACK_SEG 0x0400
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@ -16,7 +17,61 @@
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* ror it 16 bits, and as we grow the CAS, we just inc cs, and that will
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* set the right value.
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*/
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#define INIT_MCR $0xf6640000
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#define INIT_MCR $0xf6641000
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/*#include <cpu/p5/start32.inc>*/
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.org 0xfe000
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.code16
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_start: jmp _realstart
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gdt: //GDT entry 0 (null segment)
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.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
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// GDT 1
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.word 0xffff, 0x0000 /* flat code segment */
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.byte 0x0, 0x9a, 0xcf, 0x0
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.word 0xffff, 0x0000 /* flat data segment */
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.byte 0x0, 0x92, 0xcf, 0x0
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gdtptr:
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.word 3*8-1
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.long gdt /* we know the offset */
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.long 0
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_realstart:
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cli
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movw %cs, %ax
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movw %ax, %es
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.byte 0x66 /* prefix */
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.byte 0x26
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.byte 0x0f, 0x01, 0x16 /* lgdt [es:offset]*/
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.word gdtptr - EXT(_start) /* offset in segment */
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movl %cr0, %eax
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andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
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orl $0x60000001, %eax /* CD, NW, PE = 1 */
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movl %eax, %cr0
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/* invalidate the cache */
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invd
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data32 ljmp $0x8, $.Lprotected
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.Lprotected:
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.code32
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movw $0x10, %bx
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movw %bx, %es
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movw %bx, %ds
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#ifdef USE_BIG_REAL
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andb $0xfe, %al
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movl %eax, %cr0
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ljmp $0xfe00, $.Lunprotected
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Lunprotected:
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code16
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#endif
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/* WARNING: The new CALLSP code trashes the stack! */
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/* I will leave this here for now, but you should also set it later. */
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xorl %edi, %edi
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movb $0x6c, %al
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CALLSP(pci_read_dword)
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@ -26,17 +81,18 @@
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CALLSP(pci_write_dword)
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rorl $16, %ecx
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/* test 8 bit CAS */
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movb $0, (%edi)
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movb $0, 0
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movb $1, 0x800
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cmpb $0,(%edi)
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cmpb $0,0
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jnz sizeram
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inc %cl
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movb $1, 0x1000
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cmpb $0, (%edi)
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/* change the value we store each time. It makes debugging easier */
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movb $2, 0x1000
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cmpb $0, 0
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jnz sizeram
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inc %cl
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movb $1, 0x2000
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cmpb $0, (%edi)
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movb $3, 0x2000
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cmpb $0, 0
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jnz sizeram
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inc %cl
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@ -50,15 +106,24 @@ sizeram:
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/* now size the dram */
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/* you had best have at least 32M; that's as small as we go */
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/* rorr 20 the ecx value, to get row size into lsb */
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movb $0, (%edi)
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movb $0, 0
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ror $20, %ecx
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movl $0x400000, %esi
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1:
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movb $1, (%esi)
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1:
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#ifdef USE_BIG_REAL
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addr32 movb $4, %es:(%esi)
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#else
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movb $4, %es:(%esi)
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#endif
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cmpb $4, %es:(%esi)
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jne 1f
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inc %cl
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jz 1b
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rol $1, %esi
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jmp 1b
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/* size is now in esi */
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/* %ecx has setting for register */
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1:
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ror $1, %esi
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rol $20, %ecx
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/* set 4 banks. */
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orb $1, %cl
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@ -69,11 +134,11 @@ sizeram:
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* Just set 4-bank mode, and set non-zero numbers into a few places.
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* if the byte at 0 changes, you have two banks. Trivial.
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*/
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movb $0, (%edi)
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movb $1, 0x1000
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movb $1, 0x2000
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movb $1, 0x4000
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cmpb $0, (%edi)
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movb $0, 0
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movb $5, 0x1000
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movb $6, 0x2000
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movb $7, 0x4000
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cmpb $0, 0
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jz 1f /* only one bank */
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orl $80000, %ecx
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1:
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@ -109,7 +174,8 @@ pci_read_dword:
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inl %dx, %eax
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mov %eax, %ecx
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RETSP
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.org 0x01f0
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.org 0xfe1f0
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reset_vector:
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.byte 0xea # jmp to fe00:0000, where IPL
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.word 0x0000, DOC_WIN_SEG # starts in DoC
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@ -117,4 +183,5 @@ reset_vector:
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spl_vector:
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.byte 0xea # jmp to 8000:0000, where SPL
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.word 0x0000, SPL_RAM_SEG # (LinuxBIOS) starts in RAM
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pad: .byte 0, 0, 0, 0, 0, 0
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