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enable CPU pipeline and disable DRAM delay

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Li-Ta Lo 2001-01-17 08:18:38 +00:00
commit 75ac3d4d1a
1 changed files with 2 additions and 2 deletions
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4
src/northsouthbridge/sis/630/630_regs.inc
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@ -39,7 +39,7 @@ northbridge_init_table:
/* SiS 630 specific registers. See SiS 630 Registers Recommended Setting */
/* Host Control Interface */
.byte 0x50, 0x9C #
.byte 0x50, 0x9E #
.byte 0x51, 0x00 #
/* DRAM Control */
@ -48,7 +48,7 @@ northbridge_init_table:
.byte 0x54, 0x00 # 0x00 -> 66/100 MHZ, 0x08 -> 133 MHZ
.byte 0x55, 0x29 # 0x29 -> 66/100 MHZ, 0x1D -> 133 MHZ
.byte 0x56, 0x80 # 0x00 -> 66 MHZ, 0x80 -> 100/133 MHZ
.byte 0x56, 0x00 # 0x00 -> 66 MHZ, 0x80 -> 100/133 MHZ
.byte 0x57, 0x00 # 0x00 -> 100 MHZ 0x01 -> 133 MHZ
/* Pre-driver Slew Rate/Current Driving Control */