Define the QCLIB_GA_ENABLE_PD_NEGOTIATION bit in the QcLib global
attributes. This flag signals to QcLib that Power Delivery
negotiation should be performed.
BUG=b:457566143
TEST=Verify different boot modes on Google/Quenbi.
TEST=Verify that PD negotiation is skipped in normal mode.
Change-Id: Ia046f68ebeacaa1c1d9a73c4b957315c9f7b68b6
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90512
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If the section guid is CPER_SEC_PROC_IA32X64_GUID we want the x86
processor specific section instead of the generic one.
This was probably some kind copy error from the line above.
Change-Id: I6a6a885bf8ab97cb5d256513cf8134078b707d3c
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90476
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Introduce a weak function qclib_mainboard_override to allow
mainboards to customize QcLib policies or global attributes.
This hook is called from the SoC-specific QcLib initialization
path.
BUG=b:457566143
TEST=Configure QcLib policy for Google/Quenbi.
Change-Id: I0397b7138db260973ea86852cfa9f408e14d195d
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Ensure that existing flags in global_attributes are not overwritten
when enabling UART logging. Using a bitwise OR preserves any
previously set attributes.
BUG=b:457566143
TEST=Verify the QcLib global attributes.
With this CL -
```
[DEBUG] Global Attributes[0x3]..Table Entries Count[8]
```
Change-Id: Iffceb06cb800ba4c9e5c07381745cbed1fb7d550
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90509
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit updates the SSRAM memory layout in memlayout.ld to reserve
space for several new regions.
The following regions are added to the SSRAM section:
- qsee: 100K at 0x14680000
- qdss_usb_trace: 8K at 0x146A6000
- aop_imem: 8K at 0x146A8000
The memory map diagram in the comments is also updated to reflect the
reservation of aop_imem and qdss_usb_trace.
BUG=b:456953373
TEST=Able to build and boot google/quenbih.
Change-Id: I17c2a97d31cdcb81ffdd0c83d8c6d19b9a03a91b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90443
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Relocate the PRERAM_STACK region to a new address to resolve a memory
conflict with the QSEE Trust Zone environment.
Details:
- The previous location of the PRERAM_STACK starting at 0x14680000 in
SSRAM is now reserved for QC QSEE.
- This change moves the 16KB PRERAM_STACK from 0x14680000 (SSRAM) to
the available memory region starting at 0x14850000 in the BSRAM.
BUG=b:456953373
BRANCH=None
TEST=Able to build google/bluey.
Change-Id: Ifa9bc457e28b9ec21aa59c6ab9114993f23b2bc8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Implement the newly introduced PRERAM_STACK and POSTRAM_STACK macros in
the x1p42100 memory layout, addressing the memory constraints on this
SoC.
Changes
- Pre-RAM Stack: The temporary stack used before DRAM is ready is
defined using PRERAM_STACK(0x14680000, 16K) in the SSRAM region,
replacing the old generic STACK definition.
- Post-RAM Stack: The final stack is defined using
POSTRAM_STACK(0x80000000, 16K) at the start of DRAM.
- The POSTRAM_DMA_COHERENT region is shifted up to 0x80004000 to
accommodate the new 16KB post-RAM stack, avoiding memory overlap.
This guarantees a distinct and properly sized stack region for each
stage of the boot process, resolving conflicts with Trust Zone and
ensuring a clean stack transition during the RAM stage.
BUG=b:456953373
BRANCH=None
TEST=Able to build google/bluey.
w/o this patch
```
[SPEW ] stack: top_of_stack address is 0x14684000
```
w/ this patch
```
[SPEW ] stack: top_of_stack address is 0x80004000
```
Change-Id: Iccf3f99aff31a8e44386ea52b2196b49797caa79
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90405
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change prepares an alternative entry point for the ARM64
ramstage. It is written in assembly language, avoids the usage of the
stack, and overrides the program stack pointer (SP register) if the
`preram_stack` and `postram_stack` point to different addresses.
Previous Boot Flow:
- header.ld -> jump into `stage_entry` C code for ROMSTAGE onwards ->
`stage_entry` being called and followed by `main` function
Updated Boot Flow:
- header.ld -> jump into `_start` (assembly entry point) for
ramstage specifically -> Update the existing SP (stack pointer)
register if the `preram_` or `postram_` stack address is not
same -> call into `stage_entry` and follow the `main` function.
BUG=b:456953373
BRANCH=None
TEST=Able to build google/bluey.
Change-Id: I4eec24aff1c9d01180c3452a3631dd344656c771
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90403
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Refactor the stack definition macros to explicitly define separate
memory regions for the stack, addressing resource conflicts on
certain SoCs like Qualcomm x1p42100.
The original STACK macro is split into PRERAM_STACK and
POSTRAM_STACK.
Motivation:
On the Qualcomm x1p42100 SoC, the boot flow presents two
constraints for the initial stack location:
- Boot IMEM is unavailable after the ADSP is loaded.
- The existing SSRAM stack address is reserved for QC QSEE by the
Trust Zone.
Solution:
- PRERAM_STACK: Used by coreboot (e.g., till romstage) for static
stack allocation (from an alternative SSRAM or BOOT IMEM region).
- POSTRAM_STACK: Used starting from ramstage, leveraging the
DRAM-mapped memory.
This conditional split allows coreboot to manage stack memory
independently for the limited environment before DRAM is fully
initialized (ENV_ROMSTAGE_OR_BEFORE), resolving the hardware memory
conflicts while maintaining compatibility with existing code via
aliasing.
BUG=b:456953373
BRANCH=None
TEST=Able to build google/bluey.
Change-Id: I6356adc63d595f59050e6dc5961404be4a9534c0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90402
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
On the X1P42100 SoC, the System Debug Image (SDI) flow is handled by
the Always-On Processor (AOP), unlike previous architectures (e.g.,
Kodiak) which utilized a dedicated 'QcSDI' image.
Rename the memory region at 0x14699000 from 'qcsdi' to 'aop_sdi' to
accurately reflect ownership by the AOP and to align with the new
chipset architecture. This change clarifies the memory map and serves
as a prerequisite for removing legacy QcSDI artifacts once the
modern SDI flow is fully enabled.
BUG=b:456953373
TEST=Build and boot on google/quenbih target.
Change-Id: Ic5626c06decaadfd459aa21bde4efcfec92e1e47
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90505
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The script was failing when origin/main doesn't exist. Instead of
trying to detect or use a main branch, simply save the current HEAD
hash and restore it when done. This works regardless of branch names
or remote configuration.
Also improve the clean check to use git diff-files instead of
comparing to a specific branch.
Change-Id: I237de4b1e8a06fd4e1e3ef08286208c130e7a6bd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90502
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace the incorrect Intel confidential license header with the
proper BSD license header in the MemInfoHob.h file to align with
the standard licensing used for Intel FSP vendorcode.
BUG=None
TEST=None
Change-Id: I242d9abedc2910f819c70be597c5d1cbca996a2a
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This fixes the build failure for commit 0b4d41004 (mb/lenovo/sklkbl: Add
Lenovo Thinkpad X280 as a variant) caused by a discrepancy between
memory/Makefile.mk and the actual content of spd/ddr4.
Change-Id: I92a4446e7bd457a7f09a107a0cb0fe1d7a6e1de4
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90503
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This proliferates the fixes from commit e5d10e5d23, CB:90023 ("mb/
lenovo/t480: Fix headphone jack") to the other SKL/KBL Thinkpad
variants T580, T470s, and T480s. This has been only validated on the
former two machines, but since the hardware changes between the
different models appear to be minimal, it should be safe to deploy
this fix to the T480s variant blindly.
Change-Id: I1edf8dc33231b9d1e1cf2eaf3f4f296736b7be32
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The hardware of this machine is mostly identical to the already
supported Thinkpad Tx80 machines. Minor differences are the absence of
SODIMM slots (i.e. all RAM is soldered on), two fewer eDP lane pairs,
and different PCIe lane assignment.
All the hardware configuration settings (VBT, GPIO register dumps,
hda verbs, and so on) have been obtained running the latest BIOS/EC
firmware (1.59/N20ET74W, 1.15/N20HT28W). PCIe port assignments as well
as USB, RAM SPD and GPIO assignments have been cross-checked against
publicly available schematics (Finn-1).
Basic functionality has been validated on a Thinkpad X280 part number
20KF-002QUS with 16GB onboard RAM, i7-8650U CPU. The laptop has been
tested with SeaBIOS 1.17 as a payload booting either debian 13 or
Windows 10. A cursory check of the hardware (video, wifi, audio, wired
ethernet, reboot, sleep) shows no issues. This patch also includes a
fix for the headphone jack detection that's been already validated
on the Thinkpad T480 with commit e5d10e5d23 ("mb/lenovo/t480: Fix
headphone jack").
Change-Id: Ia8e6c40b200dee240d08d79253fbbe0842882a80
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90254
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Logs such as "DRAM-K: calibration failed: status = 1" give little
information about the failure reason. Add get_status_string() and use it
to print the return status as a string.
Change-Id: If20282f0de7ba8ce884d0016fe8da1dc93a33ea4
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90484
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Optimize the `sdram_size` function by caching the calculated SDRAM
size in a static variable. This prevents redundant calls to
`mtk_dram_size()` or `mem_chip_info_total_density_bytes()` if the size
has already been determined, improving performance in scenarios where
`sdram_size` is called multiple times.
BUG=none
TEST=emerege-tanjiro coreboot
Change-Id: I0ca0df80ee9cb781a5bb6d55ee28a2c1153be0ad
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90485
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This patch enables MTE (Memory Tagging Extension) for the MediaTek
MT8196 SoC.
During `soc_init`, it calculates the required size and start address for
the MTE tag storage based on the physical DRAM size. It then calls
`booker_mte_init` to initialize the MTE hardware with the calculated
start address.
Later, during memory initialization, `bootmem_platform_add_ranges` uses
`bootmem_add_range_from` to reserve the calculated memory region for
MTE tag storage, preventing it from being used for other purposes.
BUG=b:438666196
TEST=Check cbmem log.
[DEBUG] booker_mte_init: MTE tag addr 0x460f70000
...
[DEBUG] 17. 0000000460f70000-000000047ffeffff: TAG STORAGE
[DEBUG] 18. 000000047fff0000-000000047fffffff: RESERVED
Change-Id: I7caa4fde4f314261383a68e942b0e3fb06c6184b
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90144
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The Armv9-A architecture introduces the Memory Tagging Extension (MTE),
which uses a dedicated memory region for tag storage.
This patch adds a new memory type, BM_MEM_TAG, to allow for the proper
accounting and reservation of this memory region. This ensures that the
payload, e.g. depthcharge, can correctly identify and utilize the tag
storage area.
BUG=b:438666196
Change-Id: I2f6d2b3c2c1a8e1f0e9b2c3d4e5f6a7b8c9d0e1f
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This patch introduces a new function, bootmem_add_range_from, which
allows adding a memory range of a specific type only if it is carved
out from a range of another specific type. This is useful for cases
where memory needs to be allocated from a pre-defined region.
The function checks if the target range is fully contained within a
range of `from_tag` before marking it as `new_tag`. Error reporting
is included to log cases where the allocation is not possible.
BUG=b:438666196
Change-Id: Icfdb5ef9114572c075be6ef4e57d00151300a17a
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90469
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GCC generates correct code for __builtin_bswapXX() on all architectures,
including ArmV4. It seems that whatever bug caused this to not work back
in commit 879ea7fce8 ("endian: Replace explicit byte swapping with
compiler builtin") has been fixed now. We can eliminate the swabXX()
functions and simplify the code.
All instances that had been calling these functions directly should have
been using real endianness conversions anyway.
Change-Id: I19713fd009aa5c0e01c4a42e0cf012364d6bed60
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90438
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
In preparation for the upcoming DSI dual channel support, pass dsi_regs
and mipi_tx_regs to DSI functions that need to access these registers.
BUG=b:424782827
TEST=util/abuild/abuild -x -t GOOGLE_SAPPHIRE -a
BRANCH=none
Change-Id: Ia0c9051148e38a7703119f800d417f2f8b52f78a
Signed-off-by: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90446
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add dsi_register_v3.h to define dsi_regs struct for mt8196, and add
dsi_reg.h to define mipi_tx_regs struct. Unlike other SoCs, mt8196
has dsi1 and mipi_tx1 registers in order to support DSI dual channel.
BUG=b:424782827
TEST=util/abuild/abuild -x -t GOOGLE_SAPPHIRE -a
BRANCH=none
Change-Id: I2b541c89a007f380de482bffa86aca60c351b526
Signed-off-by: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90451
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Move dsi0 variable definition to dsi_register_v*.h to be closer to the
register struct definition. This also allows us to define dsi1 for
mt8196 at the same place as dsi0 in a future patch. The dsi1 variable
cannot be defined in dsi_common.h because not all MediaTek SoCs using
the header have the DSI1_BASE register.
BUG=b:424782827
TEST=util/abuild/abuild -x -t GOOGLE_SAPPHIRE -a
BRANCH=none
Change-Id: I643f8d0317d0fb8bd8ea7bf8870ec99051c35c1b
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90452
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The soc/dsi.h header contains SoC-specific dsi and mipi_tx register
definitions, which are not needed for SoCs not supporting MIPI DSI
panels (such as mt8195). To decouple the generic display.c (used for
both eDP and MIPI panels) from those register definitions, move the
mtk_dsi_init() declaration and MIPI_DSI_* enums to display_dsi.h.
This allows us to remove the unused soc/dsi.h for mt8195.
BUG=b:424782827
TEST=util/abuild/abuild -x -t GOOGLE_ASURADA -a
TEST=emerge-skywalker coreboot
BRANCH=none
Change-Id: I56e458ec8077ed48929637b9b5c70f08653cc73f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90449
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In an upcoming change, a dsi_regs/mipi_tx_regs argument will be added to
functions declared in dsi_common.h. Currently those structs are all
defined in soc/dsi.h. However, dsi_common.h cannot include soc/dsi.h
because soc/dsi.h already includes dsi_common.h. To solve the circular
dependency issue, move the dsi_regs/mipi_tx_regs definitions to a new
file soc/dsi_reg.h.
As mt8183/mt8186/mt8188/mt8189/mt8192 all share compatible mipi_tx_regs
definitions, create a common mipi_tx_reg_v1.h and include it in these
SoCs' soc/mipi_tx_reg.h. The mt8173 remains its own struct definition.
Also, rename MIPITX_BASE to MIPITX0_BASE in soc/addressmap.h, to have
consistent naming across all SoCs. Note that MIPITX1_BASE will be added
for mt8196 in a future patch.
BUG=b:424782827
TEST=emerge-skywalker coreboot
BRANCH=none
Change-Id: I0e2159fde5bfc358691a4b3bdebc2657f0a598a8
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90445
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The address of mipi_tx1 should be MIPI_TX1_BASE instead of
MIPI_TX0_BASE. This doesn't cause any issue in practice because mipi_tx1
is unused.
Also rename lvds_tx1/lvds_tx2 to lvds_tx0/lvds_tx1 for consistency with
the MIPI_TX0_BASE/MIPI_TX1_BASE naming.
BUG=none
TEST=none
BRANCH=none
Change-Id: I040b0a2a447333141cf6f4a012fa5d2aefd936c7
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90444
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Kabylake SoC, Intel common, and ChromeEC.
TEST=build/boot google/eve, verify CFR option functionality.
Change-Id: Id878bbd06b7eb06f12c063486fd475c742a9a13b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tidy up before adding a new CFR entry in a subsequent patch.
Change-Id: I14dc011622acad43b6a21a00d97a958ea6d3152f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90320
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Sandy/Ivybridge, C216 SB, and ChromeEC.
TEST=build/boot google/link, verify CFR option functionality.
Change-Id: I08cccf136f20018aee925372b5c181bf4b55e0cd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90319
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
IPU cameras on popp-based devices are currently not properly supported
under Windows, which causes the camera status LED to be permanently on
when using Windows. To work around this, add a CFR option to disable
the IPU camera(s) on a given board.
TEST=build/boot google/poppy (nocturne), verify camera status LED is
off when CFR option disable and Windows booted.
Change-Id: I664ecac47211350b861504c3075e524f045dbf40
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Kabylake SoC, Intel common, and ChromeEC.
TEST=build/boot google/poppy (nocturne), verify CFR option
functionality.
Change-Id: Ib63c2a105a715a540a93b6163ff7e6f86deab5d0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Skylake SoC, Intel common, and ChromeEC.
TEST=build/boot google/glados (chell), verify CFR option
functionality.
Change-Id: Ie124d69e979c7d0ca8dd119046412cb637eb04da
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from ChromeEC.
TEST=build/boot google/skyrim (frostflow), verify CFR option
functionality.
Change-Id: Ife5b20725794cdecc47f632e10421b86ceac68a5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90315
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from ChromeEC.
TEST=build/boot google/guybrush (dewatt), verify CFR option
functionality.
Change-Id: I16e80e2ba1e51617956043137cd8fee1400b57f2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90314
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from ChromeEC.
TEST=build/boot google/zork (morphius), verify CFR option functionality
Change-Id: I21f6d01ab425fb698872735bca3514ae366bcdda
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from ChromeEC.
TEST=build/boot google/kahlee (liara), verify CFR option functionality
Change-Id: I19f059f1e0c0e7c71e5e84560fe72f271d33412c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Cometlake SoC and Intel common.
TEST=build/boot google/sarien, verify CFR option functionality.
Change-Id: Id7b023cecba36ac4a5c65eb5ece05361e8881980
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Meteorlake SoC, Intel common, and ChromeEC.
TEST=build/boot google/rex (karis), verify CFR option functionality.
Change-Id: Ic115272f69c2b37263d7ca0f921e6d9eceaaa8c3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Alderlake SoC, Intel common, and ChromeEC.
Change-Id: I99505f3f8b24c2f89329a3164963e874f5861374
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
The i2c auto-detection cannot distinguish between two touchpads using
the same i2c bus and address, so drop the 'detect' flag amd implement
a user-selectable CFR option instead, defaulting to both enabled.
This will allow either touchpad to work properly under Linux, and
give the user the ability to only enable the touchpad actually present
should they wish to run Windows.
Change-Id: Iaf1406c2d10bbf10b9aea30ae1cd2b2281bfcc5d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
