Retire the short-lived special setup to share C code between them, in
favour of the common init code provided by CB:82632.
Tested on asus/p8z77-m with SeaBIOS 1.17.0.
Change-Id: I699fc08d9bfc56dad28eb20042884e979785c070
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Currently DSDT keyboard and mouse device declarations generated by
this file use IDs derived from the logical device number, in the
form of KBD# and PS2# where # is the LDN. This is far from the norm
for mainboards with only one super I/O chip, where they are named
PS2K and PS2M, which is also the names used by the much more
simplistic ASL code in drivers/pc/pc80. They also use hard coded
PNP IDs.
This patch adds two preprocessor symbols, SUPERIO_KBC_PS2KID and
SUPERIO_KBC_PS2MID, to allow these device IDs to be changed, most
likely to PS2K and PS2M. If not defined, existing naming logic is
kept.
Their _HIDs are also changed to refer to EISA ID from Kconfig,
like pc80 does. This in theory allows mainboard to change
their PNP IDs if needed. Only Lenovo laptops actually change this
from the Kconfig default, which is also the formerly hardcoded value.
Goal is to allow eliminating pc80 in favour of this when appropriate,
to avoid potential conflicts that may arise from having duplicate PS/2
devices defined.
TEST=With new symbols undefined, generated dsdt.asl did not change.
Generated dsdt.asl checked for correctness manually via temporary
manual edits, with all combinations of preprocessor controls.
Change-Id: I0dcc94c2cb09fee2e22776fd800c3435a9409c84
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
TEST=Processed dsdt.asl for mainboards using this super I/O chip
only contain changes specifically made by CB:89740.
Change-Id: Id8067e6058b650121e7c830a0cb298752a45d62c
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Make this chip use the common Nuvoton ACPI code before mainboards using
this chip begin to come online.
Change-Id: I000ebc92d1c408a865fb803a2e540ca3cca53ee7
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Define the requisite super I/O chip identities and bring in the common
ACPI code.
Change-Id: I2fbd77b0ddc5618a2da844f6e18ce483774c4cf0
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Define the requisite super I/O chip identities and bring in the common
ACPI code.
Change-Id: I1db85c8d0028a1c3e4a5582f3d0e503b71beac70
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
With few exceptions, Nuvoton super I/O chips have the same
configuration registers.
This patch provides a single set of initialization routines to set
up power loss resume, initialize keyboard, and handle switching
PS/2 port role for mainboards with only one PS/2 port.
Power loss resume handling and PS/2 port role switching can be
controlled using nvram or CFR options. Mainboards lacking such
options will need to add them separately.
The common routines support all currently in-tree Nuvoton SIO chips
except nct5104d, nct6687d, npcd378, wpcm450. They will be hooked up
in follow-up patches.
There is also SMM code to disable PS/2 keyboard wakeup before going to
S5, otherwise the system will also power up with any key on the
keyboard, which is most likely undesirable. To use this, mainboards
must set Kconfig SUPERIO_NUVOTON_PNP_BASE, add smm.c to Makefile.mk
and call it from mainboard_smi_sleep().
Update the help text of HAVE_SHARED_PS2_PORT Kconfig with the final
option name used.
TEST=Both power loss resume and PS/2 port role control work on
asus/p8z77-m with entire train of supporting patches applied.
Change-Id: Ibaddcaa2d77c5b06ddfbb6dbaac00df5e72dd4bd
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add new LDNs supported by the NCT6796D:
- 0x11: PGPIO, RI PSOUT Wake-Up
- 0x12: LED control
- 0x15: LED control 2
Change-Id: Icef4d32fad5430cbbe8ee4f3719d603361cfea95
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
The -96D is an updated version of the -91D and has additional LDNs.
This initial commit is a clone of the -91D with strings changed;
additional functionality will be added in subsequent commits.
TEST=tested with out-of-tree board Erying SRMJ4
Change-Id: I8f67c999f4076aaca52c93060a6a461dd9bcc62f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91100
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the pair of non-ramstage Nuvoton SIO PNP config mode entry/exit
functions from early_serial.c into nuvoton.h as inline functions for
both pre-RAM and SMM code use. Availability is limited to
__SIMPLE_DEVICE__ environments, or if this symbol is defined such as
when mainboards specifically request it.
Cuts outdated comment from early_serial.c and transplant its key parts
to nuvoton.h.
Remove the temporarily refactored local copies from
mb/asrock/{z87_extreme4,fatal1ty_z87_professional}.
Build tested on these two Asrock boards and asus/p8x7x-series.
Change-Id: I0238f006dd86742f937e9dcd6134ed7be566677c
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit gives the Nuvoton super I/O chip family a common ACPI
ASL code, based on nct6776 with the addition of a suspend (_PTS)
hook that disables keyboard wakeup when shutting down and records
the power state for an alternate power loss resume logic, both to
be completed by subsequent patches. This code is not active until
included by a mainboard's ASL code, and the suspend hook needs to
be invoked from there as well.
This common code supports pretty much all the nct???? super I/O chips
in tree except nct5104d, nct6687d, npcd378, wpcm450.
Change-Id: I7d8cf66e69688d1c53e4c313358174883710b374
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
sio/nuvoton will soon make use of this for common code. Move the
definition there; mainboard will only set it.
To mitigate possible conflicts in case of multiple SIO chips on
the same mainboard, rename Kconfig to add _NUVOTON_.
Change all existing references to match.
Change-Id: I8e0516411c74b162c31142b02bf5c45e4ca30a1d
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89741
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Put the most commonly shared Nuvoton SIO logical device numbers into
one central header. It will be handy when they start sharing per-LDN
setup code.
Block iasl from seeing anything other than the LDNs.
Rename the re-inclusion guard symbol as its use is no longer limited to
pre-RAM stages.
It references NCT677x because that reference is hidden in every single
Nuvoton SIO chip datasheet in my possession.
Change-Id: Ibf01c0e0ffdecbedc34df62b582e3be0c5c0a852
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Found on many Asus P8x7x series mainboards, NCT5535D is a 64-pin LPC
super I/O chip with no publicly available datasheet. However, it appears
to share the same silicon as NCT6779D. With only half the pins of 6779,
it does not have parallel port, serial port B, or GPIOs 1 and 6.
This patch adds header and Kconfig option for 5535, and adapts 6779
code to also supply C code to 5535 as well.
asus/p8z77-v_lx2 still builds once modified for this chip, but is not
tested further.
Change-Id: I3fe0dd6fc3010a50b781ca7c5c39ea73b91978a5
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85834
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adds long overdue power loss resume support to nct6779d using
code from nct5572d.
Change-Id: I91bf01a176716b97c6ca6a841c68cd3d4a39d23d
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88701
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on similar NCT6687D chip. Obtained the NCT6686D EC Space
Specification datasheet from Nuvoton via email request. Most of
the register definitions come from the EC Space Specification,
the rest has been figured out from MSI MS-7D25 BIOS.
Change-Id: I162f9d4067f0cba1d22d6cb5f98b68987719c038
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Allow the power state after failure to be set using an option backend
if used, otherwise fall back to the Kconfig selection. This is a
noop for all it8772f boards unless they enable an option backend, in
which case that option setting is now functional, whereas before it
would have been ignored for the Kconfig selection.
TEST=build/boot google/panther with various power state after fail
Kconfig selections.
Change-Id: I1988d70fe27a287cd2cc91dbb905c243c24c816d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87383
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the programming of the power state after power failure to the ITE
EC common code, in order to unify and extend to other ITE SIO chips.
The implementations in the it8720f and it8728f are functionally
identical, so take the "best" style elements of both, using clear
variable names and defines for registers rather than magic values.
Change-Id: I4b7e9455e964320f35997fdf04a515b942e030c7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
This patch adds support for the Fintek f81966d SuperIO,
which is very similar to the fintek/f81866d.
Datasheet:
- Name: F81966D/A, Release Date: Oct 2023, Version: V0.21P
BUG=NA
TEST=Customer platform with F81966D, verified with 'superiotool -de'
Change-Id: Ibe3987b6e15eb07b92d7f5a7de2bd511de85e2f7
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87198
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
The hardware monitor provides access to its address space via the base
address stored in LDN 0x4 at index 0x60/0x61. There is no need to set
the configuration mode here, since the registers in the LDN are not
programmed.
Change-Id: Ic27c9eee5a58727a70fc0ebe60a643f45a418d36
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The HWM port is +5 to the base address stored in LDN 0x4 at index
0x60/0x61. Take this rule into account when configuring the monitor,
as it was done for Fintek SIO chips in the superiotool utility [1].
[1] commit d92745b
TEST=Run coreboot on the motherboard with the Fintek F81966 chip (which
is architecturally compatible) with pnp_write_hwm5_index() in the HWM
initialization code:
- the fans are regulated correctly;
- superiotool prints the values of the configuration registers updated
during initialization.
Change-Id: If39400e56a7d0792a5bc8f312c29dd5e98a0b2d3
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87273
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Harrie Paijmans <hpaijmans@eltan.com>
Found on tiny firewall appliance from Chinese company named "Topton"
with Intel N100 SoC. This system is fanless so all we need is the
ability to use serial output (RS232 in RJ45 form-factor, called
"Cisco-style" at address 0x3f8), which is working.
Change-Id: I9c27f52785d294a6f7c315b8df47d4dd5b389414
Signed-off-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84176
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This properly supports power_on_after_fail setting on affected
mainboards.
Tested on GA-H61M-S2PV
Change-Id: I3dcc4f032bc5f629fb916c4122beb8dc096bab20
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Since a generic ITE GPIO driver is available and in use, the existence
of chips-specific drivers no longer make sense. Remove the dead code
in favor of generic GPIO driver.
Change-Id: I7e031d12192af4bd47923d87c1d02c64f9c851a2
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83497
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enables the driver for ITE SIOs supporting the GPIO register layout
(confirmed with datasheets for the modified ITE SIO Kconfigs, SIOs
with unavailable datasheets are unmodified).
Other ITE SIOs may select it with SUPERIO_ITE_COMMON_GPIO_PRE_RAM
and must then provide the number of GPIO sets specific to a chip
via SUPERIO_ITE_COMMON_NUM_GPIO_SETS.
Change-Id: I0868ff3e9022b135c21f4c1a6746d6440b8f0798
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add a generic driver to configure GPIOs and LEDs on common ITE
SuperIOs. The driver supports most ITE SuperIOs, except Embedded
Controllers. The driver allows configuring every GPIO property
with pin granularity.
Verified against datasheets of all ITE SIOs currently supported by
coreboot, except IT8721F (assumed to be the same as IT8720F),
IT8623E and IT8629E.
Change-Id: If610d2809b56c63444c3406c26fad412c94136a5
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83355
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Based on the non-public "ITE IT8659E-I Preliminary Specification V0.7.2
(For H Version)".
TEST=Initialize IT8659E on the new Protectli platform
Change-Id: I11657ec6e1c880f0cee247071486a904a92bb7a1
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Introduce HAVE_SHARED_PS2_PORT Kconfig for this Super I/O to have
mainboards indicate if they have one shared PS/2 port on the rear
panel. On these boards (where a Y-cable cannot allow both
keyboard and mouse to work off the same port), if a PS/2 keyboard is
not present, SIO should be configured to swap its role to mouse, to
allow the OS to find and initialize any mouse connected.
Supporting code will come in a separate patch. Idea is to condition
them on this Kconfig.
Change-Id: I156b15c6ba233cbe8b9ba4d2cfbca6836ad7483a
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82631
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
<stdio.h> header is used for input/output operations (such as printf,
scanf, fopen, etc.). Although some input/output functions can manipulate
strings, they do not need to directly include <string.h> because they
are declared independently.
Change-Id: Ibe2a4ff6f68843a6d99cfdfe182cf2dd922802aa
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82665
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to datasheet, the enable bit for direct I/O access to GPIO
lines is at CR30[3] of LDN 8, not [0] as currently coded.
Change-Id: Id2f997aebc36a2fcaa8c3763f324d3b288f785d2
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81926
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A function to disable the PME# output was added. This is required to
set up the SuperIO on the "HP Pro 3500 Series" mb.
Change-Id: I94f023ba6eb24b5fb1c5e0b30eb65738f50a87eb
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81589
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The 3VSBSW# signal can now also be disabled again which is necessary to
power components down properly in SMM when entering S5. In such cases
the signal will be enabled only in the SMM S3 handler.
Change-Id: I8535176908ec39e9916774135e028cbc7c203474
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81588
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
A number of ITE SIOs support "special fan control vectors", which
effectively allow non-linear fan speed control. This is for example used
by the vendor firmware of the "HP Pro 3500 Series".
The special vector registers won't be written to until the mb's
devicetree configures `FAN_VECX.tmp_start != 0`.
Change-Id: I93df2b5652fc3fde775b6161fa5bebc4a34d5e94
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The it8772f is now configured by the much better common code that is
used for other chips in the family as well. This mainly concerns the EC,
the GPIO functionality was not moved to common as it currently lacks a
sane abstraction in any codebase.
The datasheets of the it8772e(f) and it8728f (for reference) were
studied and verified against the common code, adding exceptions where
needed.
Change-Id: Ic4d9d5460628e444dc20f620179b39c90dbc28c6
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81310
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add Kconfig option for full-speed setting. Some variants do not support
the full-speed at limit configuration (IT8772F). Keep it enabled for all
current variants that use the common EC code as it was previously
enabled unconditionally - datasheets weren't revisited individually.
Change-Id: Icf24ea1c4f41771a18803957456f0aeba0e51b13
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81525
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix warning for disabled thermal inputs.
Fix warning for PECI thermal inputs if one was set up previously.
Depending on the mb, the superio will not go through power-on reset and
retain its registers. Do not trigger a warning if the current register
value aligns with the desired value. Don't return early if some input is
already configured for PECI, simply overwrite the configuration.
Both warnings were observed while porting the "HP Pro 3500 Series" mb.
Change-Id: Ibabe1b1ef55f2acb2074eceb535ec684bffc8155
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Some LDNs do not implement the activate bit at all, e.g. ITE GPIO LDNs
are an example where the LDN is always active. The pnp_generic.asl can
be used to describe the GPIO LDN resources configured by the platform,
however the register 0x30 is always 0 for these LDNs, so OS will not
claim the reported resource for the GPIO device, because _STA will
return inactive LDN.
Add SUPERIO_PNP_NO_DIS macro to generate _STA method returning an
always active LDN and skip _DIS generation. Define the SUPERIO_PNP_NO_DIS
for SIOs which use the pnp_generic.asl preserving the previous states,
except the ITE GPIO LDNs.
Change-Id: Ieb827fdffe7660b875cba6ca99b0560b4cab66b4
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80496
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Unfortunately, the datasheet for IT8629E is not public. Therefore, we
will use the functionally closest chip (i.e. IT8728F) as a reference
and try to reverse-engineer where necessary.
IT8629E seems to be very similar to IT8628E (again, no public
datasheets), as the chip id is 0x8628.
Known differences:
- LDN 0x08 (functionality is unknown)
- Supports 6 fans
Change-Id: I44d0377da11f0e118017caa4357012df9373b322
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80344
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This renames bus to upstream and link_list to downstream.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Macros can be confusing on their own; hiding commas make things worse.
This can sometimes be downright misleading. A "good" example would be
the code in soc/intel/xeon_sp/spr/chip.c:
CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev,
This appears as CHIP_NAME() being some struct when in fact these are
defining 2 separate members of the same struct.
It was decided to remove this macro altogether, as it does not do
anything special and incurs a maintenance burden.
Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
The .inc suffix is confusing to various tools as it's not specific to
Makefiles. This means that editors don't recognize the files, and don't
open them with highlighting and any other specific editor functionality.
This issue is also seen in the release notes generation script where
Makefiles get renamed before running cloc.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I41191f6971bdd8ecff2c56f4bfa2b57c87530b83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80076
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
In commit 0a0945c6a2 (sio/nuvoton/npcd378: Use acpi_device_path_join),
some oversights were made. Instances of "strconcat(scope, ..." should be
replaced with "..._join(dev->bus->dev, ..." instead of "..._join(dev, ...".
On HP 8200 USDT, this fixes ACPI error like this on resume from S3:
ACPI BIOS Error (bug): Could not resolve symbol [\_SB.PCI0.LPCB.SIO0.L040.RMFG], AE_NOT_FOUND (20230628/psargs-330)
ACPI Error: Aborting method \_GPE._L08 due to previous error (AE_NOT_FOUND) (20230628/psparse-529)
ACPI Error: AE_NOT_FOUND, while evaluating GPE method [_L08] (20230628/evgpe-511)
RMFG seems to be a typo of PMFG made in that same commit.
Change-Id: Ifffa7ad72cfdb644c8b5147132a5fd56511ed33b
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Used by the OptiPlex 3020/7020/9020:
- EMI and Runtime registers work
- UART1 works (including IRQs)
- PS/2 keyboard and mouse untested
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Change-Id: I9323198f1139cd0c3dd37f977ae7693b721654f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
