superio/nuvoton: Add common ACPI ASL code
This commit gives the Nuvoton super I/O chip family a common ACPI ASL code, based on nct6776 with the addition of a suspend (_PTS) hook that disables keyboard wakeup when shutting down and records the power state for an alternate power loss resume logic, both to be completed by subsequent patches. This code is not active until included by a mainboard's ASL code, and the suspend hook needs to be invoked from there as well. This common code supports pretty much all the nct???? super I/O chips in tree except nct5104d, nct6687d, npcd378, wpcm450. Change-Id: I7d8cf66e69688d1c53e4c313358174883710b374 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Keith Hui
Matt DeVillier
parent
7273a5b932
commit
02c57577f3
1 changed files with 214 additions and 0 deletions
214
src/superio/nuvoton/common/acpi/superio.asl
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src/superio/nuvoton/common/acpi/superio.asl
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Include this file into a mainboard's DSDT _SB device tree and it will
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* expose the NCT677x SuperIO and some of its functionality.
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*
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* It allows the change of IO ports, IRQs and DMA settings on logical
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* devices, disabling and reenabling logical devices.
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*
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* LDN State
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* NCT677X_PP Implemented, untested
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* NCT677x_SP1 Implemented, untested
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* NCT677x_SP2 Implemented, untested
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* NCT677x_KBC Implemented, untested
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* 0x308 GPIO Implemented, untested
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* 0xb HWM Implemented, untested
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*
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* Controllable through preprocessor defines:
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*
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* SIO identities
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* SUPERIO_DEV Device identifier for this SIO (e.g. SIO0; required)
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* SUPERIO_CHIP_NAME Chip name (@)
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* SUPERIO_FULL_CHIP_NAME Unicode device name (@)
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* SUPERIO_PNP_BASE I/O address of the first PnP configuration register (@)
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* Items with @ are required if multiple SIO chips are being used.
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*
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* Functionality exposed if defined:
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* NCT677X_SHOW_PP Parallel port
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* NCT677X_SHOW_SP1 Serial port 1
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* NCT677X_SHOW_SP2 Serial port 2
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* NCT677X_SHOW_KBC Keyboard controller
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* NCT677X_SHOW_GPIO GPIO by I/O support
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* NCT677X_SHOW_HWM Hardware monitor
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*/
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#include <superio/nuvoton/common/nuvoton.h>
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/* Get SUPERIO_PNP_BASE from Kconfig if not redefined */
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#ifndef SUPERIO_PNP_BASE
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#define SUPERIO_PNP_BASE CONFIG_SUPERIO_NUVOTON_PNP_BASE
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#endif
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#include <superio/acpi/pnp.asl>
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#undef PNP_DEFAULT_PSC
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#define PNP_DEFAULT_PSC Return (0) /* no power management */
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#define ENABLE_KEYBOARD_WAKEUP SKWK
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#define POWER_LOSS_LAST_STATE PLSF
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Device(SUPERIO_DEV) {
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Name (_HID, EisaId("PNP0A05"))
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Name (_STR, Unicode(SUPERIO_FULL_CHIP_NAME))
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Name (_UID, SUPERIO_UID(SUPERIO_DEV,))
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/* SuperIO configuration ports */
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OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 2)
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Field (CREG, ByteAcc, NoLock, Preserve)
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{
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PNP_ADDR_REG, 8,
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PNP_DATA_REG, 8,
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}
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IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve)
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{
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Offset (0x07),
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PNP_LOGICAL_DEVICE, 8, /* Logical device selector */
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Offset (0x30),
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PNP_DEVICE_ACTIVE, 1, /* Logical device activation */
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ACT1, 1, /* Logical device activation */
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ACT2, 1, /* Logical device activation */
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ACT3, 1, /* Logical device activation */
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ACT4, 1, /* Logical device activation */
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ACT5, 1, /* Logical device activation */
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ACT6, 1, /* Logical device activation */
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ACT7, 1, /* Logical device activation */
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Offset (0x60),
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PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */
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PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */
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Offset (0x62),
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PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */
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PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */
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Offset (0x64),
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PNP_IO2_HIGH_BYTE, 8, /* Third I/O port base - high byte */
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PNP_IO2_LOW_BYTE, 8, /* Third I/O port base - low byte */
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Offset (0x70),
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PNP_IRQ0, 8, /* First IRQ */
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Offset (0x72),
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PNP_IRQ1, 8, /* Second IRQ */
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Offset (0x74),
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PNP_DMA0, 8, /* DRQ */
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Offset (0xe0), /* Config register 0xe0 etc. */
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,6,
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ENABLE_KEYBOARD_WAKEUP, 1,
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Offset (0xe6),
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,4,
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POWER_LOSS_LAST_STATE, 1,
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Offset (0xf2),
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SPME, 1, /* Enable PME */
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,7,
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OPT3, 8,
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OPT4, 8,
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,8,
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OPT6, 8,
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OPT7, 8
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}
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Method (_CRS)
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{
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/* Announce the used I/O ports to the OS */
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Return (ResourceTemplate () {
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IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 1, 2)
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})
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}
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Method (SIOS, 1, NotSerialized)
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{
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ENTER_CONFIG_MODE(NCT677X_ACPI)
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if (Arg0 == 5)
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{
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ENABLE_KEYBOARD_WAKEUP = 0
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/* Log "power off" state */
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POWER_LOSS_LAST_STATE = 1
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}
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EXIT_CONFIG_MODE()
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}
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Method (SIOW, 1, NotSerialized)
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{
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}
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#undef PNP_ENTER_MAGIC_1ST
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#undef PNP_ENTER_MAGIC_2ND
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#undef PNP_ENTER_MAGIC_3RD
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#undef PNP_ENTER_MAGIC_4TH
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#undef PNP_EXIT_MAGIC_1ST
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#undef PNP_EXIT_SPECIAL_REG
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#undef PNP_EXIT_SPECIAL_VAL
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#define PNP_ENTER_MAGIC_1ST 0x87
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#define PNP_ENTER_MAGIC_2ND 0x87
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#define PNP_EXIT_MAGIC_1ST 0xaa
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#include <superio/acpi/pnp_config.asl>
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#ifdef NCT677X_SHOW_PP
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#undef SUPERIO_PNP_HID
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#undef SUPERIO_PNP_LDN
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#undef SUPERIO_PNP_IO0
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#undef SUPERIO_PNP_IRQ0
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#undef SUPERIO_PNP_DMA
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/*
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* The extra code required to dynamically reflect ECP in the HID
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* isn't currently justified, so the HID is hardcoded as not
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* using ECP. "PNP0401" would indicate ECP.
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*/
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#define SUPERIO_PNP_HID "PNP0400"
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#define SUPERIO_PNP_LDN NCT677X_PP
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#define SUPERIO_PNP_IO0 0x08, 0x08
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#define SUPERIO_PNP_IRQ0
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#define SUPERIO_PNP_DMA
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#include <superio/acpi/pnp_generic.asl>
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#endif
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#undef SUPERIO_UART_DDN
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#undef SUPERIO_UART_PM_REG
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#ifdef NCT677X_SHOW_SP1
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#undef SUPERIO_UART_LDN
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#define SUPERIO_UART_LDN NCT677X_SP1
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#include <superio/acpi/pnp_uart.asl>
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#endif
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#ifdef NCT677X_SHOW_SP2
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#undef SUPERIO_UART_LDN
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#define SUPERIO_UART_LDN NCT677X_SP2
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#include <superio/acpi/pnp_uart.asl>
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#endif
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#ifdef NCT677X_SHOW_KBC
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#undef SUPERIO_KBC_LDN
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#undef SUPERIO_KBC_PS2M
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#undef SUPERIO_KBC_PS2LDN
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#define SUPERIO_KBC_LDN NCT677X_KBC
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#define SUPERIO_KBC_PS2M
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#include <superio/acpi/pnp_kbc.asl>
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#endif
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#undef SUPERIO_PNP_HID
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#undef SUPERIO_PNP_DMA
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#ifdef NCT677X_SHOW_HWM
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#undef SUPERIO_PNP_LDN
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#undef SUPERIO_PNP_IO0
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#undef SUPERIO_PNP_IO1
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#undef SUPERIO_PNP_IRQ0
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#define SUPERIO_PNP_LDN NCT677X_HWM_FPLED
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#define SUPERIO_PNP_IO0 0x08, 0x08
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#define SUPERIO_PNP_IO1 0x08, 0x08
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#define SUPERIO_PNP_IRQ0
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#include <superio/acpi/pnp_generic.asl>
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#endif
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#ifdef NCT677X_SHOW_GPIO
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#undef SUPERIO_PNP_LDN
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#undef SUPERIO_PNP_IO0
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#undef SUPERIO_PNP_IO1
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#undef SUPERIO_PNP_IRQ0
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#undef PNP_DEVICE_ACTIVE
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#define PNP_DEVICE_ACTIVE ACT3
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#define SUPERIO_PNP_LDN 8
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#define SUPERIO_PNP_IO0 0x08, 0x08
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#include <superio/acpi/pnp_generic.asl>
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#endif
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}
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