Update the charging flow to support a transition from slow charging
to fast charging based on the battery threshold.
Key changes:
- Pass boot_mode to launch_charger_applet() to allow mode-specific
power management.
- In LB_BOOT_MODE_LOW_BATTERY_CHARGING, if the battery is above the
critical threshold, issue an AP power-off to trigger a transition
from slow to fast charging mode.
- Update handle_low_power_charging_boot() to default to slow charging
for low-battery charging boots.
BUG=b:497622018
TEST=Verified Bluey correctly switches from slow charging to fast
charging once critical battery threshold is exceeded.
Change-Id: Ic65ab99360496c92a91795fce1352159066ab94e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add option variables to allow user override of PL1/PL2 via CMOS/CFR,
which can be exposed by mainboards. Add the ability to lock the power
levels set to prevent the OS/userspace tools from meddling. Add a
CFR form for the lock option which mainboards can use.
TEST=build/boot google/beltino with PL1/2 and lock options exposed,
verify changes reflected in cbmem and by reading MSR/MCHBAR.
Change-Id: I3db0a44c1e8982348026fa9e66123fd41a0f9884
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91876
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Expose PL1 and PL2 overrides in the Power CFR form, allowing users to
adjust the values within safe limits. Expose CFR option to lock the
programmed values.
TEST=build/boot Fizz, verify adjusted values reflected in cbmem log,
MSR 0x610, and MCHBAR registers.
Change-Id: Iab7b2cdf815cadfbc93e1d8395380706243ec203
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add helper functions to determine sku type and default PL2 value; the
latter will be exposed and used externally in a subsequent commit.
Rename and remove variables to clarify and simplify the function.
Defines for FIZZ_PSYSPL2_U22/U42 are renamed to clarify that they are
the max adapter power for those SKUs; PsysPL2 is set to 90% of these
values via the SET_PSYSPL2() macro.
Change-Id: I504b2dcedbf3817351516b051effc2c70082854d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91882
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When PL1 exceeds the SKU TDP, program MSR_PLATFORM_POWER_LIMIT (0x65c)
long-term (PsysPL1) to the same value.
This prevents the long-term system power from becoming a choke point
when raising the package PL1.
Change-Id: I85a604467ccbede84a668117ad588ac75b742a70
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add option-backed overrides for PL1 and PL2, to allow for runtime
configuration, with fallback to board programmed values. Clamp PL2
to at least PL1.
Add an option to control setting the lock bit, to prevent OS or user
tools from overriding the desired power limits.
Add a CFR object for setting the lock bit, but not for the PL1/2
overrides, as the desired values there are board specific.
TEST=tested with rest of patch train
Change-Id: I7194df93e0602b4e00d1d39e44cb0b0ed2582cb9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91846
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aralguppe, Sowmya <sowmya.aralguppe@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Enable/disable the sink sensor for DAM port during power on/off.
BUG=b:491325845
TEST=Verify the configuration on power on/off on Google/Quartz.
Change-Id: Ib00e1cc1c86bafb19cde24c7faa624d3e6d00db8
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91890
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a standalone script to detect new contributors between two local
git refs and print the names and count. Support --update to merge new
names into AUTHORS in sorted order, and --full to include email plus
earliest commit date/hash/subject.
Functionality extracted from genrelnotes script; script largely
generated by Cursor AI.
Change-Id: I5841f68d04522f84e871a80778e0038fd6cba5a9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91888
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for the new memory Micron MT62F1G32D2DS-031RF WT:C using
spd-3.hex, and MT62F2G32D4DS-031RF WT:C using spd-6.hex
DRAM Part Name ID to assign
K3KL6L60GM-MGCT 0 (0000)
H9JCNNNBK3MLYR-N6E 1 (0001)
H58G56CK8BX146 2 (0010)
MT62F1G32D2DS-026 WT:B 3 (0011)
K3KL8L80CM-MGCT 3 (0011)
MT62F1G32D2DS-031RF WT:C 4 (0100)
MT62F2G32D4DS-031RF WT:C 5 (0101)
BUG=b:493068113
TEST=Normal boot
Change-Id: I03afd40346890e99b2be83dfabc1c3e95ef0bf8c
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: hualin wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
DRAM Part Name ID to assign
H58G56BK8BX068 7 (0111)
BUG=b:496028135
TEST=build nissa coreboot
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Change-Id: Ibf816767acf2d1a2b087365615a68d15bededb98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Only enable GPIO_EN_FP_RAILS when booting in LB_BOOT_MODE_NORMAL.
This avoids powering the FP MCU in non-normal boot modes such as
low battery or charging scenarios where FP functionality is not
required.
BUG=b:494962574
TEST=Verified by normal boot and check FP LED.
Change-Id: I7dca803fb3414f7b6b12eb9a8f284a3f1b7b6d87
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91898
Reviewed-by: wen zhang <zhangwen6@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
improve the noise situation
When a 3.5 mm headset is connected, noise occurs during system startup
or wake-up from suspend.Setting this value "detect-us" lower should
improve the noise situation, therefore, we adjust detect_us to 100us.
BUG=b/454450799
TEST=cat /sys/kernel/debug/regmap/<sdw_dev>/registers | grep 010040
to ensure the changes take effect and improve the noise situation.
Change-Id: I0c94a1d9862f6e201b451c19f292a12fe3b9ed68
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91836
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hook up the VBIOS binary published on the amd_blobs submodule.
TEST=Graphics init works pre OS on AMD/birman+
Change-Id: I927ea1e6dd9be0c13719cf080fc7ca7505f83eba
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91854
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Apply StarFighter touchpad settings at boot and expose the tuning
controls through CFR.
Add CFR controls for vibration intensity, click force, release force,
and tracking speed. Apply the selected settings during payload boot, and
keep the touchpad controls grouped in a dedicated Trackpad menu.
Change-Id: I3a6a906f7a3ca89e42aa53bb9a4c3dd536c4fe0a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
When a mainboard has a secondary SPI flash, also referred to as
DUAL SPIROM or backup SPI flash, and a board specific recovery
mechanism for failed flash updates it might need to access the
secondary SPI flash. A use case would be syncing the MRC cache
(APOB NV on AMD), RPMC and fTPM regions to the secondary flash.
Add generic code to access the "backup" SPI flash. It assumed
that both SPI flash have the same size and same type.
The backup SPI flash chip select line is determined at runtime
so that it is the opposite of boot_device_spi_cs().
Thus when booting from CS2, CS0 will become the backup flash.
TEST=Can access and use backup flash on AMD Glinda SoC.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ied683408d36850416fc1bbfaef0c415703ff183e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The TBMC ACPI device is used by Windows ChromeEC drivers to determine
tablet mode and to enable motion sensors (accelerometer, gyroscope).
Since it's not needed/used by ChromeOS, restrict its inclusion to
non-ChromeOS builds.
TEST=build/boot Win11/Linux on frostflow, verify tablet mode and
rotation work properly, keyboard/touchpad disabled in tablet mode.
Change-Id: Iedc68797776d43f37dd97e5251cf9b9a016f1bd5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
The TBMC ACPI device is used by Windows ChromeEC drivers to determine
tablet mode and to enable motion sensors (accelerometer, gyroscope).
Since it's not needed/used by ChromeOS, restrict its inclusion to
non-ChromeOS builds.
TEST=build/boot Win11/Linux on dewatt, verify tablet mode and rotation
work properly, keyboard/touchpad disabled in tablet mode.
Change-Id: I3eeae7b453589a2253226709dd6cfcff1862ea17
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Set SYSTEM_TYPE_CONVERTIBLE for Zork-based Spin/Flip devices
so SMBIOS reports a convertible enclosure type. This enables
EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS on non-ChromeOS builds
and allows use of the vendor tablet mode ACPI.
Change-Id: I53ce5222e6b6984ef6e3b3c89ecfbae7620aaf36
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Set SYSTEM_TYPE_CONVERTIBLE for Kahlee-based Spin/Flip devices
so SMBIOS reports a convertible enclosure type. This enables
EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS on non-ChromeOS builds
and allows use of the vendor tablet mode ACPI.
Change-Id: I63d815f4cf46aee064db4a23b97c399aa334aad0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91749
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set SYSTEM_TYPE_CONVERTIBLE for the Dewatt variant so SMBIOS
reports a convertible enclosure type. This allows non-ChromeOS
builds to enable EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS and use
the vendor tablet mode ACPI.
Change-Id: I01bd8a4255b2cacc01e9eda703e88af57c8f58c7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Windows ACPI rejects devices that use both GpioInt in _CRS and a GPE in
_PRW (BSOD 0x1000D). Switch touchpad and fingerprint reader to
ACPI_GPIO_IRQ_*_WAKE so wake is expressed via GpioInt SharedAndWake
instead of a separate _PRW GPE, keeping wake support while staying
Windows-compliant.
TEST=build/boot Win11 on frostflow
Change-Id: I2ced532443e60e9cbb4e482feceab175aed9a155
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91795
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change touchpad and touchscreen IRQ from edge to level triggering across
all skyrim variants. Required for Windows driver compatibility.
TEST=build/boot Win11 on frostflow; verify touchpad/screen functional.
Change-Id: Ibbc275112536b4d555b127271ee264414d06c5cb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91794
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Windows ACPI rejects devices that use both GpioInt in _CRS and a GPE in
_PRW (BSOD 0x1000D). Switch touchpad and fingerprint reader to
ACPI_GPIO_IRQ_*_WAKE so wake is expressed via GpioInt SharedAndWake
instead of a separate _PRW GPE, keeping wake support while staying
Windows-compliant.
TEST=build/boot Win11 on dewatt
Change-Id: I04593166aad8d3c2c601ba489237a5f45be95fa2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91793
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use ACPI_GPIO_IRQ_LEVEL_LOW instead of EDGE_LOW for Elan touchpads.
Required for Windows driver compatibility.
TEST=build/boot Win11/Linux on dewatt; verify touchpad functional.
Change-Id: I712134860eee456c2c103c2ca8543020c58027f2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91792
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GPIO for the proximity sensor, which is only used by ChromeOS for
WiFi power/SAR purposes, causes an IRQ storm under Windows. Only
configure it when building for ChromeOS.
TEST=build/boot Win11 on vilboz
Change-Id: I38955f2e11c7eb412416884b4769e70dd1bde6de
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Windows ACPI rejects devices that use both GpioInt in _CRS and a GPE in
_PRW (BSOD 0x1000D). Switch touchpad and fingerprint reader to
ACPI_GPIO_IRQ_*_WAKE so wake is expressed via GpioInt SharedAndWake
instead of a separate _PRW GPE, keeping wake support while staying
Windows-compliant.
TEST=build/boot Win11 on morphius
Change-Id: I2a47b8435fb19ec39d19e09967defa91ae58a85b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91790
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change Raydium and ELAN touchscreen IRQ from edge to level triggering
across berknip, dalboz, ezkinil, trembyle, and vilboz variants.
Necessary for Windows driver compatibility.
TEST=build/boot Win11/Linux on ezkinil; verify touchscreen functional.
Change-Id: I126589f9412f405d69961919bf61c4c60f623676
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This commit introduces initial support for PCI Express on the
Qualcomm Calypso SoC.
Key changes include:
- Selecting `CONFIG_PCI` in Kconfig to enable general PCI subsystem
support for this SoC.
- Selecting `CONFIG_NO_ECAM_MMCONF_SUPPORT`, indicating that this
platform will not use the standard MMCONFIG ECAM for PCI
configuration space access. An alternative mechanism will be required.
- Adding `../common/pcie_common.c` to the ramstage build if `CONFIG_PCI`
is enabled, incorporating common PCIe helper functions.
BUG=b:496650089
TEST=Able to build google/calypso.
Change-Id: I813e0811e9fd5b6ceefbf72635998a26536987c8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Implement the sku_id() function for the Mensa mainboard to replace
the existing placeholder.
The SKU ID is retrieved from the Chrome EC using the common
google_chromeec_get_board_sku() interface. To optimize performance and
avoid redundant SPI transactions to the EC, the value is cached
after the initial read.
BUG=b:496650089
TEST=Build and boot on Mensa; verify SKU ID is correctly reported in
cbmem logs.
Change-Id: Ibaef20913e8043a02b2468d1157ac1a4a2087fc6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit adds the `clock_init()` function for the Qualcomm calypso
SoC. This function is now called at the beginning of
`bootblock_soc_init()` to enable SoC-specific clock setup early in the
boot process.
The `clock_init()` function definition is currently a placeholder
and will be populated with the required clock configurations in
subsequent changes.
BUG=b:496650089
TEST=Able to build google/mensa.
Change-Id: I3886670348e998b3d80d33643e2256af4eb47fd7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The bootblock requires early initialization of the Quad-SPI (QSPI)
controller to enable reading firmware from flash memory.
This commit adds calls to `quadspi_init()` with a 75 MHz bus clock
and `qupv3_fw_init()` within `bootblock_soc_init()`. This ensures
that the essential hardware for flash access and related QUPv3
functions are properly configured during the boot process.
BUG=b:496650089
TEST=Able to build google/mensa.
Change-Id: I225485cf601c62b1ba695eb61f786a1360790f41
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91903
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the default Kconfig values for the google/mensa mainboard
to specify the correct hardware instances/buses used for various
peripherals as per mensa schematics (dated 03/10).
Changes:
- TPM I2C bus set to 0x01.
- ChromeEC SPI bus set to 0x16.
Removes previous TODO placeholders.
BUG=b:496650089
TEST=Successfully built google/mensa.
Change-Id: Ic377be3dc165bf1c1e19031994d87ea45d6c2dc0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch adds QUP-SE entries as applicable for the Qualcomm Calypso
SoC.
This includes:
- Add new entries for QUPV3_3 SEs.
- Update base addresses for all QUP-SEs.
- Base GPIO pin function assignments.
- Definition and GPIO mapping for relevant QUP Serial Engines (SEs).
- GPIO mapping for the QSPI interface.
Additionally, update GPIO PINS for QSPI and UART.
BUG=b:496650089
TEST=Successfully built google/mensa.
Change-Id: Iab0eecc08d11d99d2534010af86217e6cc2a1961
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Update the default Kconfig values for the `soc/qualcomm/calypso`
to specify the correct hardware instances/buses used for various
peripherals as per datasheet for mensa (dated 03/10).
Changes:
- Boot SPI flash bus set to 26.
- Console UART instance set to 21.
Additionally, remove previous used TODO placeholders.
BUG=b:496650089
TEST=Successfully built google/mensa.
Change-Id: I89a298b13eb7761f1767d054c09eafdb3daf0927
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit introduces basic support for the google/mensa mainboard,
based on the Qualcomm Calypso SoC.
Changes:
- Add placeholder mainboard callbacks to enable control flow from /lib
and Qualcomm SoC code.
- Populate the bluey mainboard directory with a copy of the bluey
codebase, removing SoC/mainboard-specific implementations.
This provides a minimal working build for google/mensa, allowing
upstream builders to compile the mainboard. This facilitates easier
verification of subsequent changes.
BUG=b:4966500890
TEST=Successfully built google/mensa with Qualcomm Calypso SoC.
Change-Id: Id30a766c1bc6b37a6d35ba933c207951ab83f4d1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit introduces a basic SoC framework for the Qualcomm
Calypso SoC enabling initial build integration.
Key changes:
- Add placeholder SoC callbacks to facilitate control flow from /lib
and Qualcomm common code.
- Populate the calypso SoC directory with a copy of the X1P42100
codebase, with SoC-specific implementations removed.
This provides a foundational structure for Calypso development
within the `soc/qualcomm/calypso` directory, ensuring the upstream
builder can successfully compile the SoC code.
This allows for incremental development and integration.
Reference Document: Calypso Hardware Register Description
BUG=b:496650089
TEST=Successfully built google/mensa with the Qualcomm Calypso SoC.
Change-Id: Iabbbf26c9e08906db2be024911061837fdf83bd9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91892
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The X1P42100 SoC and future Qualcomm platforms support more than two
QUPV3 wrappers. This patch extends the common Qualcomm drivers to
handle a third wrapper (QUP_WRAP3).
Details:
- clock.c: Update clock_configure_dfsr_table() to support wrap3.
- qupv3_config.c: Initialize the third wrapper if defined.
- addressmap.h: Add QUP_WRAP3_BASE defines for sc7180, sc7280,
and x1p42100 (defaulting to 0 for older chips).
Change-Id: I58ed310c65319f26ec029071d170237130d9ba19
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The generic config name SOC_QUALCOMM_BASE is too broad and could
potentially conflict with other Qualcomm SoC families or common
code.
Rename it to SOC_QUALCOMM_X1P42100_BASE in both Kconfig and
Makefile.mk to ensure the configuration is explicitly scoped to
the X1P42100 series.
Change-Id: Idb74ad5ecd6180e3b472a5d007157fcc76f3e89d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91891
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, display_startup() is called unconditionally during
mainboard_init(). For normal boot paths, this can lead to unnecessary
latency (40ms) issues.
Modify the initialization flow to:
1. Initialize display early only for low-battery or off-mode
charging paths to ensure the user sees the charging UI.
2. Defer display initialization for all other modes to a new
mainboard_late_init() function.
3. Use a static flag (display_init_done) to ensure display_startup()
is only executed once regardless of the entry point.
TEST=Verified bluey still shows charging animation when low on
battery and boots to OS normally. Able to save 40ms of the boot time.
Change-Id: Id6bdda90b7f67c13cd7334ba17131a8243af0cdb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91845
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The URL must have the .pdf extension now, otherwise gets a 404.
Add a note on later revisions of Sure Start.
Change-Id: I00ab30b461795c672890a21d1fb2af929865c822
Signed-off-by: Daniel Maslowski <info@orangecms.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Khalifa Rouis <khalifa@missingno.tech>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Default-enable CONFIG_TCG_OPAL_S3_UNLOCK for Star Labs boards so NVMe
OPAL devices can be unlocked via SMM on S3 resume when the payload
provides the password for the current sleep cycle.
TEST=build/boot adl/hz and starfighter/mtl with TCG enabled, suspend,
and verify SSD can be read after resume.
Change-Id: Ic3d9611295b1bdf9ea49cd6d4d6c924f8eafd746
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91046
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
OPAL S3 unlock may run before an RTD3 NVMe is powered on. When the
storage root port uses the RTD3 ACPI driver, trigger the OPAL unlock SMI
at the end of _ON once the port has powered the device.
Do not rely on _ON being invoked during S3 resume. Always trigger a
best-effort unlock during the coreboot resume path. If the NVMe init
path fails (rc=1), keep the sleep cycle armed so a later trigger (e.g.
RTD3 _ON) can retry the unlock.
TEST=tested with rest of patch train
Change-Id: If83b59973ad878c31e19d146fec8bdbb6406ec2f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91416
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Provide common entry points for the OPAL S3 unlock feature and wire them
into the generic x86 SMM and S3 resume code.
- Add opal_s3_smi_{apmc,sleep,sleep_finalize} helpers.
- Call these helpers from the default weak mainboard SMI hooks when
CONFIG(TCG_OPAL_S3_UNLOCK) is enabled. This keeps the feature usable
without forcing boards to implement new SMI handlers.
- Trigger the SMM unlock on S3 resume from arch/x86/acpi_s3.c.
Select SMM_OPAL_S3_STATE_SMRAM so the secret is persisted across SMM
handler reload. Add a delay and retry loop before unlock, and restore
NVMe BAR0 if the device loses PCI config state across S3.
The SMM side continues to whitelist only the OPAL service and unlock
APMC commands and fails closed if any invariant is violated.
TEST=tested with rest of patch train
Change-Id: I86a44760a189219a95914bd3549997880fb0242b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91045
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fixes commit "util/amdfwtool: Move APOB_NV quirk to amdfwtool.c".
Allow the AMD_BIOS_NV_ST and AMD_BIOS_APOB_NV to end at 16MiB.
Fixes a build failure when the region is last in the FMAP.
Change-Id: Icfa5b74e98223ff5864299d4e9a2d23606935b80
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91820
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Applying the attribute silences the following error and allows
compilation with GCC 15.2.
error: initializer-string for array of 'char' truncates NUL terminator but destination lacks 'nonstring' attribute
Change-Id: I33cf3219f34e297de03f67d3e73058b10930c9f8
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
PSP supports A/B updates of the PSP directory structure. This
is unrelated to VBOOT's A/B update scheme. At boot the PSP
structures of partition A are verified. If A is found corrupted
partition B will used to read in the PSP files. x86 software can
then fix the A partition and switch back to the A partition.
Add functions to get, set and toggle the active boot partition used
on the next boot.
Change-Id: Ia7f2eedae5b277745cb34a0761bd1a8b61441695
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Implement the red i-dot LED in the ThinkPad logo at the display lid.
On warm reboot the LOGO LED isn't automatically turned on by the EC.
Turn it on in the ramstage code, which allows to see when the reboot
has happened. (Similar to PWR LED; see change ID 88998)
Further testing on other devices running H8 EC is required!
TEST=LOGO LED is on after warm reboot on Lenovo T440p.
Reference: https://ch1p.io/t440p-leds-control-linux/#list-of-leds
Related: https://review.coreboot.org/c/coreboot/+/88998
Change-Id: I2ebba5a4c1ffc38f0c2e1b24793e4a252cc171bd
Signed-off-by: Christian Schrötter <cs@fnx.li>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91837
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
