Matt DeVillier 881fe9cef6 soc/intel/alderlake: Add cpuid_to_adl mapping for Core 3 N350 SoC ... Add a mapping for the Core 3 N350 SoC, which has a MCH with PCI DID 0x4617, 8 efficiency cores, and a 7W TDP. This eliminates an error when setting power limits due to the missing entry: [ERROR] unknown SA ID: 0x4617, skipped power limits configuration TEST=build/boot starlabs/starlite_adl with ADL-N Core 3 N350 SoC. Change-Id: Ibd701ec5589a9a023a5538f470ff234a23249b45 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/88018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>		2025-06-11 08:40:51 +00:00
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amd	soc/amd/glinda: Don't let OS put debug UART into D3	2025-06-04 18:00:06 +00:00
cavium
example/min86
ibm/power9
intel	soc/intel/alderlake: Add cpuid_to_adl mapping for Core 3 N350 SoC	2025-06-11 08:40:51 +00:00
mediatek	soc/mediatek/mt8189: Add support for USB port 0 reset	2025-06-09 07:02:01 +00:00
nvidia
qualcomm	soc/qualcomm/x1p42100: Enable basic PCIe support	2025-05-30 04:21:29 +00:00
rockchip
samsung
sifive
ti
ucb/riscv
xilinx