Sowmya V 6186399a0f soc/intel/pantherlake: Add CD clock frequency control support ... This change adds support for configuring higher CD Clock frequencies for VGA SOL initialization during the Pre-Memory phase. This feature allows BIOS to request specific display core clock frequencies when VGA support is enabled during MRC training. The VgaInitControl field in IGPU_PEI_PREMEM_CONFIG has been extended to include BIT6-7 for CD Clock frequency selection: * 0: No higher CD Clock required * 1: 442 MHz * 2: 461 MHz BUG=b:458353982 TEST=Build and boot fatcat/lapis, verify display initialization. Change-Id: I82fae0d21bb83ed26aad73b830ed15fcd626a9ae Signed-off-by: Alok Agarwal <alok.agarwal@intel.com> Signed-off-by: Sowmya V <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90795 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2026-02-19 02:44:50 +00:00
..
amd	soc/amd/cezanne/acpi: Move SMN accessor to DSDT	2026-02-17 14:23:06 +00:00
cavium
example/min86
ibm/power9	soc/power9/rom_media.c: find CBFS in PNOR	2025-08-28 20:14:01 +00:00
intel	soc/intel/pantherlake: Add CD clock frequency control support	2026-02-19 02:44:50 +00:00
mediatek	soc/mediatek/common: Combine dsi_cmdq_size register writes	2026-01-25 19:06:22 +00:00
nvidia	treewide: Move mipi_panel_parse_commands() to commonlib	2026-01-14 09:38:36 +00:00
qualcomm	soc/qualcomm/x1p42100: Add support to invoke LPASS Init	2026-02-12 17:23:48 +00:00
rockchip	treewide: Move mipi_panel_parse_commands() to commonlib	2026-01-14 09:38:36 +00:00
samsung
sifive
ti
ucb/riscv
xilinx