Michał Żygowski 4d1d27fcf3 vendorcode/amd/opensil: Add Turin OpenSIL ... Add Turin OpenSIL driver and submodule pointing to turin_poc branch of github.com/openSIL/openSIL repository. Change-Id: Idd6d4e78a055926061de330da620c943b42a50a7 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/88711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>		2026-01-28 13:32:33 +00:00
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cezanne	soc/amd/*/memmap.c: Report FCH MMIO regions as reserved	2025-12-01 13:56:56 +00:00
common	Makefile.mk: Remove "crt0" dead code	2026-01-25 19:05:42 +00:00
genoa_poc	soc/amd: add ACPI code for I3C controller	2025-12-01 19:41:52 +00:00
glinda	soc/amd/glinda,picasso/xhci: use XHCI_GEVENT define	2026-01-24 17:10:09 +00:00
mendocino	soc/amd: add ACPI code for I3C controller	2025-12-01 19:41:52 +00:00
phoenix	soc/amd: add ACPI code for I3C controller	2025-12-01 19:41:52 +00:00
picasso	soc/amd/glinda,picasso/xhci: use XHCI_GEVENT define	2026-01-24 17:10:09 +00:00
stoneyridge	soc/amd/stoneyridge: Generate SATA ACPI registers at runtime	2025-11-14 16:28:19 +00:00
turin_poc	vendorcode/amd/opensil: Add Turin OpenSIL	2026-01-28 13:32:33 +00:00