Configure CPU root port 1 to operate at PCIe Gen2 speed instead of
the default Gen3. This change addresses signal integrity issues on
the PCIe link that prevent reliable operation at Gen3 speeds.
TEST=Booted on mc_rpl1 and verified CPU RP1 operates at Gen2 speed
with `lspci -vv -s 01:00.0 | grep LnkSta`. Output shows
`LnkSta: Speed 5GT/s (downgraded), Width x2`
Change-Id: I35650d46d4c2ac6942b2e68a4fd23fe875bd0c10
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89765
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
29faf77d4a