NyeonWoo Kim 244a34b3d0 cpu/x86/mp_init: Refactor ICR wait logic ... Extracted ICR wait logic into a new function 'icr_wait_timeout'. Change-Id: Ie48899f7afb125061fd7efd44c83f5775c05d254 Signed-off-by: NyeonWoo Kim <knw0507@naver.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/88788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com>		2025-08-19 20:56:58 +00:00
..
acpi	drivers/crb/tpm: Add new method to retrieve base address	2025-07-02 16:15:09 +00:00
arch	arch/x86/memcpy: Fix undefined behaviour	2025-08-19 20:55:24 +00:00
commonlib	commonlib/include/commonlib: Add volatile qualifier	2025-07-22 16:30:38 +00:00
console
cpu	cpu/x86/mp_init: Refactor ICR wait logic	2025-08-19 20:56:58 +00:00
device	device/device_util: Fix format specifier for DEVICE_PATH_GICC_V3	2025-08-15 19:00:14 +00:00
drivers	tree: Replace union {0} initializers with {} for C23 compliance	2025-08-11 16:40:34 +00:00
ec	sb/intel: Convert get_gpio() to gpio_get()	2025-07-25 17:05:12 +00:00
include	include: Make DRAM an explicit region	2025-08-16 01:58:58 +00:00
lib	soc/common/smbus: Support reading SPD5 hubs for DDR5	2025-08-02 01:47:44 +00:00
mainboard	mb/google/bluey: Add QuenbiH board	2025-08-18 22:02:05 +00:00
northbridge	device/dram: Rename 'USE_DDRx' config options	2025-07-25 17:03:02 +00:00
sbom	sbom: Fix build with merged bootblock and romstage	2025-07-07 14:29:29 +00:00
security	security/vboot: Back up CMOS data later boot phase	2025-06-05 13:36:19 +00:00
soc	soc/qualcomm/x1p42100: Use 4K for memory region alignment	2025-08-18 02:04:07 +00:00
southbridge	sb/intel/common/gpio: Move register defines	2025-08-07 17:48:10 +00:00
superio	src/superio/nuvoton: Add HWM initialization code	2025-06-11 13:31:25 +00:00
vendorcode	vc/intel/fsp: Update PTL FSP headers to FSP 3272_04	2025-08-19 11:29:21 +00:00
Kconfig	security/vboot: Back up CMOS data later boot phase	2025-06-05 13:36:19 +00:00