Configure the right GPIOs for finger print sensor interrupt and reset
lines.
As per the schematics GPP_C8 is for sensor interrupt and GPP_C9
is for sensor reset.
BUG=none
BRANCH=none
TEST=none
Change-Id: I0ef25ab9ca0f1215ea70d450bb7cff38ae4debb7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2ea12e5ce0
Original-Change-Id: Ib25c68ec2fe20b1302b6170d67ceab7e8cca1a83
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18389
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/451359
One very long line has to be wrapped to be shorter than 80 characters to
satisfy the lint scripts.
Note, that this gets rid of the brackets ().
BUG=none
BRANCH=none
TEST=none
Change-Id: I096cf6151a68e30a9b438d4b5526d72f0faacd94
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3329262eca
Original-Change-Id: Ie98eff360ebc5b68ce496edc15eb2d9fddcac868
Original-Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Original-Reviewed-on: https://review.coreboot.org/18556
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/451358
Status:
- The primary PCIe 16x slot works:
It was tested with a GPU compatible with nouveau
- USB and audio are not very reliable
- The ethernet card is not seen with lspci
- The secondary pcie16x slot isn't working:
When plugging a GPU inside, it's not seen with lspci
- SATA works: The board fully boots GNU/Linux
- Serial doesn't work
- Populating the RAM slots might have to follow
the recommended memory configuration that is described
in the mainboard manual in order to be able to boot.
Note that when running the shutdown command, the default
boot firmware will rewrite part of the boot flash before
powering off the machine.
Flashing coreboot internally from the default boot fimrware can
still work, if the power plug is removed after running flashrom.
BUG=none
BRANCH=none
TEST=none
Change-Id: I63e576c9e0b32a97b6575d2ef35448c22ad2889a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 420d3a93c1
Original-Change-Id: I934de521d0acceb7770f23b2ae15c31a67ae73eb
Original-Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Original-Reviewed-on: https://review.coreboot.org/16931
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/451272
These definitions do not require AGESA.h include,
and we will eventually remove agesawrapper.h files.
BUG=none
BRANCH=none
TEST=none
Change-Id: If0e0310f276c5d72fac69f959a935f0d4ac7aa76
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d610c5823c
Original-Change-Id: I1b5b78409828aaf2616e177bb54a054960c3869f
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18588
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/451271
The size of the array did not match that of the actual
allocation. Furthermore, the tables are written as
part of set_pci_irqs() in hudson/pci.c.
Also the removed code was never reached runtime, as it is
only executed on ACPI S3 resume path that is currently
disabled.
BUG=none
BRANCH=none
TEST=none
Change-Id: I39342e03eec9c71b2584bb078a6811193e302869
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 627d790651
Original-Change-Id: If1c47d53a7656bdff40d93fc132c8c057184ae46
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18587
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/451270
This file is only static defines.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1518d84653ef98d3b00f9a43f48a656eb2e68afc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 50bb68f2b6
Original-Change-Id: Id50a0eba1ce240df36da9bd6b2f39a263fa613df
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18585
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Philippe Mathieu-Daud <f4bug@amsat.org>
Reviewed-on: https://chromium-review.googlesource.com/451268
The current elog implementation has two event types defined for 0xa7,
apparently the result of divergent coreboot trees on chromium where
some events were added to ARM systems but not upstreamed until later.
Fix this by moving ELOG_TYPE_THERM_TRIP to be 0xab, since the current
elog parsing code in chromium is using ELOG_TYPE_SLEEP for 0xa7.
BUG=b:35977516
TEST=check for proper "CPU Thermal Trip" event when investigating a
device that is unexpectedly powering down.
Change-Id: I3dbba826383f9dd911f910d8f9e6db7433463a10
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6cbd3980ab
Original-Change-Id: Idfa9b2322527803097f4f19f7930ccbdf2eccf35
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18579
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/451264
Move all common MSRs as per IA SDM into a common location
to avoid duplication.
BUG=none
BRANCH=none
TEST=none
Change-Id: Idfb8d874d83e38c112a07bea24909b6493717cfd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c2fd0a2114
Original-Change-Id: I06d609e722f4285c39ae4fd4ca6e1c562dd6f901
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18509
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/451261
It seems that we should only ever run at 900mV on center logic.
Changing it to 950mV before might have just masked over problems that
are now fixed.
BRANCH=none
BUG=chrome-os-partner:56940
TEST=on kevin, run
stressapptest -M 1536 -s 1000
Change-Id: I5a09b1b403df800396bb2f2e8c76d14a4519d44a
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/388068
Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Tested-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Lin Huang <hl@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
In the safety considerations, we should make sure the slot of SD is
enabled first, since we want to the power switch of corresponding is
powered up.
The different boards have the different power switch for sdmmc.
Some power switch IC need turn on delay for long time.
let's move the slot power of SD to romstage and avoid explicit delays
or per-board.
BRANCH=none
BUG=b:35813418, b:35573103
TEST=check the signal for children of gru, and boot up from sd card.
Change-Id: I48ab543143d3de9be46608fc12d78e09decf8d79
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/447076
Reviewed-by: Julius Werner <jwerner@chromium.org>
Currently, when using `iasl` 20140926-32 [Oct 1 2014] from Debian 8
(Jessie/stable), the build of the Lenovo X60 fails due to syntax errors.
ASL 2.0 supports `<<`. For consistency, right now, coreboot still uses
the old syntax. So use `ShiftLeft` instead, which also fixes the build
issue with older ASL compilers.
BUG=none
BRANCH=none
TEST=none
Change-Id: I030413bf10db3d8b2435d1fd55e96c7a9a0c457d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: db94213640
Original-Change-Id: Id7e309c31612387da3920cf7d846b358ac2bdc71
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/18520
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <f4bug@amsat.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/450377
Support for voltage margining is dependent on the platform.
Enabling voltage margining puts additional constraints for
the SLP_S0# to be asserted and hence moving to S0ix state.
If the platform PMIC/VR supports PCH voltage reduction,
voltage marigining can be enabled.
Use the UPD provided by FSP to enable/disable voltage margining.
BUG=none
BRANCH=none
TEST=none
Change-Id: I5d75e043dadf8adc6ed1e7a7800dd525ff76116b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0da186c3ff
Original-Change-Id: Iea214e9d7d6126e8367426485c6446ced63caa66
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18469
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/450241
This is selected by default and not overwritten anywhere else for this
board.
BUG=none
BRANCH=none
TEST=none
Change-Id: I69fe18bb51cac9b5914f1d51055a8182a5424c5f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d55ea7b69e
Original-Change-Id: I0f803e130366ee322163f7bb6fa16cac75f5416e
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18541
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/450240
As we drive both channels with the same speed,
chan0dll and chan1dll are the same.
BUG=none
BRANCH=none
TEST=none
Change-Id: I64c2fe3d14c3f174448863ac37ac8ba21f09a369
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 44a3066015
Original-Change-Id: I7253ea9ea66396c536c82d63c67fecb041681707
Original-Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Original-Reviewed-on: https://review.coreboot.org/18472
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/450238
AGESA AmdInitEarly() reconfigures the lapic timer in a way that
conflicts with lapic/apic_timer.
This results in an endless loop when printk() is called after
AmdInitEarly() and before the apic_timer is initialized.
This patch forces a reconfiguration of the timer after
AmdInitEarly() is called.
Codepath of the endless loop:
printk()->
(...)->
uart_tx_byte->
uart8250_mem_tx_byte->
udelay()->
start = lapic_read(LAPIC_TMCCT);
do {
value = lapic_read(LAPIC_TMCCT);
} while ((start - value) < ticks);
[lapic_read returns the same value after AmdInitEarly()]
BUG=none
BRANCH=none
TEST=none
Change-Id: I32003d5fc62bcd2a54a91dc536d0e43315642c28
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b2bb6ad2a7
Original-Change-Id: I1a08789c89401b2bf6d11846ad7c376bfc68801b
Original-Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/17924
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/450237
This reverts commit fec8872c9d.
The commit introduced a regression which is causing MC4 failures
when 8 RDIMMs are populated in a configuration with a single CPU
package. Using just 4 RDIMMs, the failure does not occur.
After reverting the commit, I tested configurations with
1 CPU (8x8=64GB) and 2 CPU packages (16x8=128GB) using an
Opteron 6276. The MC4 failures did not occur anymore.
BUG=none
BRANCH=none
TEST=none
Change-Id: I0a508bff03899c8b7bd7429bce653a7bea94bef0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 610d1c67b2
Original-Change-Id: Ic6c9de84c38f772919597950ba540a3b5de68a65
Original-Signed-off-by: Daniel Kulesz <daniel.ina1@googlemail.com>
Original-Reviewed-on: https://review.coreboot.org/18369
Original-Tested-by: build bot (Jenkins)
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://chromium-review.googlesource.com/449827
The newly assigned ACPI ID for coreboot is 'BOOT'
http://www.uefi.org/acpi_id_list
Use this new range of ACPI IDs of "BOOTxxxx" for coreboot specific
ACPI objects instead of the placeholder range of "GOOGCBxx".
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia3bfdec7652d4cf7c8647a7e3b0a1a324666b0af
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 59eddac6ad
Original-Change-Id: I10b30b5a35be055c220c85b14a06b88939739a31
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18521
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/449826
Fix a typo that was introduce in commit 696ebc2d (Broadwell/Sata:
Add support for setting IOBP registers for Ports 2 and 3.) [1].
Setting one of the SATA port 3 IOBP setting was using the value from
the port 2 register.
On the purism/librem13 (on which SATA port 3 is tested), this change
doesn't seem to affect anything, as that typo wasn't exhibiting any
visible problems anyways.
[1] https://review.coreboot.org/18408
BUG=none
BRANCH=none
TEST=none
Change-Id: I872b03d4d4d28ae77d1cfe315da6a336c555817b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 601aa313a6
Original-Change-Id: I3948def5c0588791009c4b24cbc061552d9d1d48
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/18514
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/449825
Follow commit 7676730 (mb/lenovo/x60: Remove PCI reset code from
romstage). The PCI reset was copied from code specific for Roda
RK886EX and Kontron 986LCD-M. It is not needed on the MacBook.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1a8fb6acddf19dfe8cbfcc9ef74684d8b7ac6950
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a154a910cb
Original-Change-Id: I22dac962e8079732591f9bc134c1433f5c29ff4e
Original-Signed-off-by: Axel Holewa <mono-for-coreboot@donderklumpen.de>
Original-Reviewed-on: https://review.coreboot.org/18502
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/449824
struct dimm_info has all the parameter types defined in stdint.h
file. So including it.
BUG=none
BRANCH=none
TEST=Build and boot KBLRVP
Change-Id: Ifca96aea794f3bdb6e150bb5e61301d0169e5e8e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c16d389363
Original-Change-Id: I707523749ecf415e993b460f9613eae7be859c34
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18471
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <f4bug@amsat.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/449822
Save SMBIOS memory information from FSP MEM_INFO_DATA_HOB in CBMEM.
Add function dimm_info_fill() which populates SMBIOS memory
information from FSP MEM_INFO_DATA_HOB data.
BUG=chrome-os-partner:61729
BRANCH=none
TEST=Build and boot KBLRVP to verify the type 17 DIMM info coming in
SMBIOS table from Kernel command "dmidecode".
Change-Id: I489ff93622c18183115b9d7a0cb62a22a96bdc3e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e13b77564f
Original-Change-Id: I0fd7c9887076d3fdd320fcbdcc873cb1965b950c
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18418
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/449821
Add the MemInfoHob.h provided by FSP v1.6.0 for aid in parsing the
MEM_INFO_DATA_HOB.
BUG=chrome-os-partner:61729
BRANCH=none
TEST=Build and boot KBLRVP
Change-Id: I0f6d691fcc4c3be900108dda8fb1d8cc7d3c3144
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9e54978f6e
Original-Change-Id: Ia2b528ba4d9f093006cc12ee317d02e7f3e83166
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18326
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/449820
thinkpad_acpi expects a SSMS method to turn on/off the mute LED
and a MMTS method to turn on/off the microphone mute LED. With
these methods implemented the driver can correctly sync the LEDs
with the corresponding statuses.
There seems to be two different bits to mute the audio in the
Lenovo H8 EC:
* AMUT, used internally (for example to disable the audio before
entering S3).
* ALMT, controllable by the OS, which also toggles the mute LED
(if present).
Tested on a X220T and on a X201.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6a33511266f67aa2337b83673ea7a990f33df6a9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 068edc1c52
Original-Change-Id: I578f95f9619a53fd35f8a8bfe5564aeb6c789212
Original-Signed-off-by: Nicola Corna <nicola@corna.info>
Original-Reviewed-on: https://review.coreboot.org/18329
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/449819
Currently, the USB ports are still powered during S3, so turning
them off may reduce the power consumption.
Note that, when the USB Always on feature is enabled, the USB
ports are always powered, regardless of the USBP state.
This patch also disables the audio, as it might consume some
power or generate some noise.
Both the USB power and the audio are reenabled by coreboot during
the poweron.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iab4aff2c38ee494a5db3b0804f154ecbd4955f75
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 435d307415
Original-Change-Id: If0431b1315fffef2e372e7023f830a66bb7fddae
Original-Signed-off-by: Nicola Corna <nicola@corna.info>
Original-Reviewed-on: https://review.coreboot.org/18464
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://chromium-review.googlesource.com/449818
On the models that support it (like the X220) the LED pulses, on
the others (like the X201) the LED powers off.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibcb9d2bfe1c1d93d3af828f1eac7438f38ae2d56
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b1ffff7dab
Original-Change-Id: I2ac7dbc30609179e4ca5fc0a7b06763431fe3344
Original-Signed-off-by: Nicola Corna <nicola@corna.info>
Original-Reviewed-on: https://review.coreboot.org/18325
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://chromium-review.googlesource.com/449817
thinkpad_acpi expects a MHKG method which returns the current
state of the tablet mode switch shifted left by 3. If such
method is not found, subsequent laptop/tablet mode events are
ignored.
Tested on a X220T.
BUG=none
BRANCH=none
TEST=none
Change-Id: I0f07edd24cb8edef45ae62df7edc06fcc1aeb68c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 47f87bd93f
Original-Change-Id: Ic9ffea2ffe507b3692d1dd7411c52b813ec32146
Original-Signed-off-by: Nicola Corna <nicola@corna.info>
Original-Reviewed-on: https://review.coreboot.org/18328
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://chromium-review.googlesource.com/449816
This timeout is probably needed on all devices with Lenovo H8 embedded
controllers so set the default there.
BUG=none
BRANCH=none
TEST=none
Change-Id: I8c622291d18ebe5433d10f839abb76dfbf92fead
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f77d6ba911
Original-Change-Id: I830ab1894f7c0f10f55c82e398becf44d810852d
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18274
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://chromium-review.googlesource.com/449815
RAMD_ID_1 moves to PAD_DSI_TE and RAM_ID_2 moves to PAD_RDP1_A on Rowan.
BUG=chrome-os-partner:62672
BRANCH=none
TEST=emerge-rowan coreboot
Change-Id: I64fd29de607a0b360d355fd3724e3a649adc658b
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/448397
Reviewed-by: Julius Werner <jwerner@chromium.org>
The differential signal of DQS need keep low
level before gate training. RPULL will connect
4Kn from PADP to VSS and a 4Kn from PADN to
VDDQ to ensure it.But if it have PHY side ODT
connect at this time,it will change the DQS
signal level.So it need disable PHY side ODT
when do gate training.
BRANCH=None
BUG=None
TEST=boot from bob
Change-Id: I33cf743c3793a2765a21e5121ce7351410b9e19d
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/448278
Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Gru/Kevin use the 933M(actually 928M for better jitter) as max sdram freq,
while bob would use 800M.
It's normal some variants can't meet 928M SI requirement and hence want
use a lower freq as spec.
BUG=chrome-os-partner:61001
BRANCH=gru
TEST=check dpll is 800M on bob
Change-Id: I46afba8d091f1489feeb20cafc44decaa81601fc
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/420208
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Shasha Zhao <Sarah_Zhao@asus.com>
Tested-by: Shasha Zhao <Sarah_Zhao@asus.com>
(cherry picked from commit eba5dff79eeedae5ff608d2d8d297ccf9c13cb55)
Reviewed-on: https://chromium-review.googlesource.com/448277
Reviewed-by: Derek Basehore <dbasehore@chromium.org>
The cr50 part on reef is connected to the SoC's UART lines. However,
when the tx signal is low it causes an interrupt to fire on cr50.
Therefore, keep the tx signal high in suspend state so that it doesn't
cause an interrupt storm on cr50 which prevents cr50 from sleeping.
BUG=chrome-os-partner:63283
BRANCH=reef
TEST=s0ix no longer causes interrupt storm on cr50. Power consumption
normal.
Change-Id: I38a14abff2f619b2b11a8f3a12ce54f61028fb48
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6295b8a57a
Original-Change-Id: Idaeb8e4427c1cec651122de76a43daa15dc54d0f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18491
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446843
Apply tuning for the PCH I2C buses on Eve based on rise/fall time
measurements that were done with a scope.
BUG=chrome-os-partner:59686
BRANCH=none
TEST=Manual testing on Eve P1 to verify that all devices on I2C
buses are still functional. Post-tuning measurement will be done
once a new firmware is released.
Change-Id: If6d7f8c77504c281bc4c0788ec0c5aa5c2607ed2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d4d6ba180d
Original-Change-Id: I3d70ff455a20ecda374d7e7fa6cd3ab15e7f2621
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18487
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446842
This patch tries to clean the code by:
o removing duplication of LPC GPIO pads
o removing incorrect definitions from devicetree
o removing irrelevant entries from FMD file
Also adds vital defaults in Kconfig so it is possible to build an image.
BUG=none
BRANCH=none
TEST=none
Change-Id: I31e2bda3b511f14fc46493f2d669b26a0329082d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6a489237d5
Original-Change-Id: Id9913f3b053189166392271152ce5300d82a7de8
Original-Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18479
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/446841
This fixes a warning that the new toolchain generates.
BUG=none
BRANCH=none
TEST=none
Change-Id: I110558801c33c2d82d56b8fd0a65b10f0e161605
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 37e30aa624
Original-Change-Id: Idf46026729a474323e74a5cf7a156bf5bc8cf026
Original-Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Original-Reviewed-on: https://review.coreboot.org/18485
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446840
BUG=chrome-os-partner:62967
BRANCH=None
TEST=Verified that touchscreen works on power-on and after
suspend-resume as well.
Change-Id: If0956204a6c6c266ea2383e29d8738b282caeb2e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 613350897d
Original-Change-Id: Id674cbcc2d524a6ed2883bf9f0e9e076890f9a85
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18466
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/446839
On my Thinkpad with an H8-compatible ENE KB9012 EC (GDHT92WW 1.52), when
the battery is nearly full and we switch from battery to AC by plugging
in the cable, the current rate will not drop to 0 immediately, but the
discharging state is cleared immediately.
This leads to the code trying to process an invalid rate value >0x8000,
leading to a displayed rate of >1000W.
This patch changes the logic to deal with these corner cases.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib0ec4d6bd5ecc128485e89449fca8021c58dd272
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9b798d7904
Original-Change-Id: Ideb588d00757f259792e5ae97729e371b63a096c
Original-Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Original-Reviewed-on: https://review.coreboot.org/18349
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446391
- Remove warnings about code using deprecated declarations such as:
plat/mediatek/mt8173/bl31_plat_setup.c: In function 'bl31_platform_setup':
plat/mediatek/mt8173/bl31_plat_setup.c:175:2: warning:
'arm_gic_setup' is deprecated [-Wdeprecated-declarations]
include/drivers/arm/arm_gic.h:44:6: note: declared here:
void arm_gic_setup(void) __deprecated;
- Disable pedantic warnings to get rid of these warnings:
In file included from plat/mediatek/mt8173/bl31_plat_setup.c:36:0:
plat/mediatek/mt8173/include/mcucfg.h:134:21: error:
enumerator value for 'MP1_CPUCFG_64BIT' is not an integer constant
expression [-Werror=pedantic]
MP1_CPUCFG_64BIT = 0xf << MP1_CPUCFG_64BIT_SHIFT
BUG=none
BRANCH=none
TEST=none
Change-Id: Ifb355b8d849d119692e0dd3ca11276ddce514089
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 80c314d64a
Original-Change-Id: Ibf2c4972232b2ad743ba689825cfe8440d63e828
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/17995
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/446390
