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UPSTREAM: google/poppy: fix finger print sensor interrupt gpio configuration

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Configure the right GPIOs for finger print sensor interrupt and reset
lines.

As per the schematics GPP_C8 is for sensor interrupt and GPP_C9
is for sensor reset.

BUG=none
BRANCH=none
TEST=none

Change-Id: I0ef25ab9ca0f1215ea70d450bb7cff38ae4debb7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2ea12e5ce0
Original-Change-Id: Ib25c68ec2fe20b1302b6170d67ceab7e8cca1a83
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18389
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/451359
This commit is contained in:
Rizwan Qureshi 2017-02-17 19:36:23 +05:30 • committed by chrome-bot
commit fcbdbd370a
1 changed files with 4 additions and 4 deletions
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8
src/mainboard/google/poppy/gpio.h
View file

@ -100,8 +100,8 @@ static const struct pad_config gpio_table[] = {
/* SML0ALERT# */ PAD_CFG_NC(GPP_C5),
/* SM1CLK */ PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */
/* SM1DATA */ PAD_CFG_NC(GPP_C7),
/* UART0_RXD */ PAD_CFG_NC(GPP_C8),
/* UART0_TXD */ PAD_CFG_NC(GPP_C9),
/* UART0_RXD */ PAD_CFG_GPI_APIC(GPP_C8, NONE, PLTRST), /* FP_INT */
/* UART0_TXD */ PAD_CFG_GPO(GPP_C9, 0, DEEP), /* FP_RST_ODL */
/* UART0_RTS# */ PAD_CFG_NC(GPP_C10),
/* UART0_CTS# */ PAD_CFG_NC(GPP_C11),
/* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */
@ -135,8 +135,8 @@ static const struct pad_config gpio_table[] = {
/* ISH_SPI_MISO */ PAD_CFG_GPI_APIC(GPP_D11, NONE,
PLTRST), /* SPKR_INT_L */
/* ISH_SPI_MOSI */ PAD_CFG_NC(GPP_D12),
/* ISH_UART0_RXD */ PAD_CFG_GPI_APIC(GPP_D13, NONE, PLTRST), /* FP_INT */
/* ISH_UART0_TXD */ PAD_CFG_GPO(GPP_D14, 0, DEEP), /* FP_RST_ODL */
/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13),
/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),
/* ISH_UART0_RTS# */ PAD_CFG_GPI_APIC(GPP_D15, NONE, PLTRST), /* MIC_IRQ_L */
/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16),
/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* DMIC_CLK1 */