This is useful, for example, in the bootblock, when a timestamp is
available which predates the call to main() in lib/bootblock.c
BUG=None
BRANCH=None
TEST=None
Change-Id: I17bb0add9f2d8721504b2e534dd6904d1201989c
Original-Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14862
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346980
Commit-Ready: Martin Roth <martinroth@chromium.org>
Tested-by: Martin Roth <martinroth@chromium.org>
Reviewed-by: Martin Roth <martinroth@chromium.org>
timestamp_cache_get() would call timestamp_cache_init() whenever it
found a timestamp cache in the TIMESTAMP_CACHE_UNINITIALIZED state.
That means that timestamp_cache_get() will never reurn a cache in the
uninitialized state.
However, timestamp_init() checks against the uninitialized state, as
it does not expect timestamp_cache_get() to perform any initialization.
As a result, the conditional branch can never be reached.
Simply remove the timestamp_cache_init() call from timestamp_cache_get().
BUG=None
BRANCH=None
TEST=None
Change-Id: I573ffbf948b69948a3b383fa3bc94382f205b8f8
Original-Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14861
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346789
Commit-Ready: Martin Roth <martinroth@chromium.org>
Tested-by: Martin Roth <martinroth@chromium.org>
Reviewed-by: Martin Roth <martinroth@chromium.org>
timestamp.c was not included in bootblock and postcar. This means that
these two stages would use the weak implementation in lib/timestamp.c
instead of the arch-specific implementation based on rdtsc.
This resulted in using timer_monotonic_get() which resets the
timestamps from 0. timer_monotonic_get() only provides per-stage
incrementing semantics on x86 because lapic implementation has
counting down values. A globally incrementing counter like rdtsc
provides the semantics like every other non-x86.
On the test configuration, the weak implementation of timestamp_get()
returned zero, resulting in wrong timestamps coming from the bootblock,
while romstage and ramstage used the arch implementation and returned
correct timestamps.
This is a great example of why weak functions are dangerous, and how
easy it is to miss subtle yet strong interactions between subsystems
and the coreboot buildsystem.
BUG=None
BRANCH=None
TEST=None
Change-Id: I656f9bd58a6fc179d9dbbc496c5b684ea9288eb5
Original-Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14860
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346788
Commit-Ready: Martin Roth <martinroth@chromium.org>
Tested-by: Martin Roth <martinroth@chromium.org>
Reviewed-by: Martin Roth <martinroth@chromium.org>
The timer emulation works by deriving a frequency based off the
Common Timer Copy with a frequency of 19.2MHz.
The desired frequency = (19.2MHz * multiplier) >> 32;
With that knowledge update the code to let the compiler perform
the necessary math based on target frequency.
BUG=None
BRANCH=None
TEST=None
Change-Id: I716c7980f0456a7c6072bbaaddd6b7fcd8cd5b37
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/14889
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346787
Commit-Ready: Martin Roth <martinroth@chromium.org>
Tested-by: Martin Roth <martinroth@chromium.org>
Reviewed-by: Martin Roth <martinroth@chromium.org>
index.html:
* Separate the sections on the main page
* Move the documentation links to the main page
* Add links for FSP 1.0 and 2.0 specifications
* Add link for UEFI specifications
* Add link to MinnowBoard MAX coreboot
fsp1_1.html:
* Use Integration instead of Documentation
SoC/quark.html:
* Move documentation to main page
* Update build instructions for CorebootPayloadPkg
* Remove FatPkg since it is now part of edk2 tree
* Add source location for QuarkFspPkg
* Add build instructions for QuarkFspPkg
TEST=None
Change-Id: I48bd1bf98a6d8bc43bdd3b4c51dfd119a1e0f61b
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14882
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 2d96be6484)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346628
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Having CFLAGS with -Os disables -falign-function, for
unlucky builds this may delay entry to ramstage by 600ms.
Build the low-level IO functions aligned with -O2 instead.
Change-Id: Ice6781666a0834f1e8e60a0c93048ac8472f27d9
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/14414
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry-picked from commit 08311f5033)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346627
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
As of now FSP-M can not be relocated and it can not be instructed
to use a specific resource for temporary memory. As result coreboot
is forced to use CAR layout dictated by default FSP-M configuration.
Change CAR size to 1MiB, link romstage at such CAR address so it
doesn't overlap with FSP-M's default heap/stack.
Change-Id: I56f78f043099dc835e294dbc081d7506bfad280d
Original-Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14804
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
(cherry-picked from commit 0e46307574)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346623
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Currently, StackBase field doesn't work and changing it from default
value leads to crash.
Change-Id: Id3f3ea9a834d0c04a8381938535109d6a729cca2
Original-Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14803
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry-picked from commit 5ede3d8cce)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346622
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If '-b' isn't passed when adding an FSP file type to CBFS allow
the currently linked address to be used. i.e. don't relocate the
FSP module and just add it to CBFS.
Change-Id: I61fefd962ca9cf8aff7a4ca2bea52341ab41d67b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/14839
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
(cherry-picked from commit 493ec92eb3)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346617
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add I2C chip initialization for the Galileo boards.
TEST=Build and run on Galileo Gen2
Change-Id: Ib5284d5cd7a67de2f3f98940837ceb2aa69af468
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14829
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 15843bdad0)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346616
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the I2C driver.
TEST=Build and run on Galileo Gen2
Change-Id: I53fdac93667a8ffb2c2c8f394334de2dece63d66
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14828
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit ac690b1e9b)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346615
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Set the base address and enable the GPIO and legacy GPIO controllers.
Call the mainboard routine to initialize the GPIO controllers.
TEST=Build and run on Galileo Gen2
Change-Id: I06aed5903d6655d2a0948fb544cf9e0db68faa26
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14827
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 3f0fe68c4b)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346612
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add Kconfig to configure coreboot for a specific Galileo board.
Configure the GPIOs for the specific Galileo board.
TEST=Build and run on Galileo Gen2
Change-Id: I992460d506b5543915c27f6a531da4b1a53d6505
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14826
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 274d20a065)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346611
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
strlen(string) was on the negative side of the selection operator, the
side where string is NULL.
Change-Id: Ic421a5406ef788c504e30089daeba61a195457ae
Reported-by: Coverity Scan (CID 1355263)
Original-Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Original-Reviewed-on: https://review.coreboot.org/14867
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
(cherry-picked from commit 0ba307f0fe)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346610
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This configures and enables SPI interface #5 used for EC
communications on Gru/Kevin.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=with the appropriate depthcharge change it is possible to trigger
booting Chrome OS from the SD card by pressing '^U' on Gru
keyboard at the right time.
Change-Id: I99883daa60562ccddfaeb858c1957d497f05a501
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346632
Set board GPIOs as required and add their description into the
appropriate section of the coreboot table, to make them available to
depthcharge.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=with the rest of the patches applied it is possible to use
keyboard on Gru, which indicates that the EC interrupt GPIO is
properly configured. The rest of the pins will be verified later.
Change-Id: I82be76bbd3211179e696526a34cc842cb1987e69
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346631
This defines mux settings for the GPIO bank responsible for SPI
interface #5.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=with the rest of the patches applied it is possible to
communicate with the EC on gru: pressing Ctrl-U during boot
allows to start Chrome OS from the SD card.
Change-Id: Idf55c069b05492f8cdc204a8c273e39a19a3aef3
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346630
Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
The same GPIOs are used on both platforms, definitions are added an a
new .h to make it easier to re-use them across the code.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=panel backlight still enabled on Gru as before. The rest of the
GPIOs are used in the upcoming patches.
Change-Id: I1a6c5b5beb82ffcc5fea397e8e9ec2f183f4a7e0
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346219
Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Add register access routines for the GPIO and legacy GPIO controllers.
TEST=Build and run on Galileo Gen2
Change-Id: I0c023428f4784de9e025279480554b8ed134afca
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14825
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 083da160af)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346527
Commit-Ready: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Add LPC_DEV and LPC_FUNC symbols
TEST=Build and run on Galileo Gen2
Change-Id: I8485e2671af439f766228d4eaf9677c2ff8ff3f6
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14880
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 4c56a58f63)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346526
Commit-Ready: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Replace # define with #define
Align the right hand column to prepare for further expansion
TEST=Build and run on Galileo Gen2
Change-Id: Ie4d9fb56d52d7291be5523d31c1d3aa51f94dcd6
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14879
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 76684bf75b)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346525
Commit-Ready: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
This fixes compilation of coreboot on Glados
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BRANCH=none
TEST=emerge-glados coreboot works again
BUG=none
Change-Id: Ibaae68192a3dc070c6ecf79223da4a1e1f18b352
Reviewed-on: https://chromium-review.googlesource.com/346198
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Luigi Semenzato <semenzato@chromium.org>
The bootblock gets slightly too big, so adjust the space assigned to
it.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
BUG=none
BRANCH=none
TEST=emerge-nyan coreboot works again.
Change-Id: If494e49fb60c11e01ca780c84036ebf24459628c
Reviewed-on: https://chromium-review.googlesource.com/346492
Reviewed-by: Martin Roth <martinroth@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Simplify the union references to enable Coverity to properly process
the routine.
Found-by: Coverify CID 1349854
TEST=Build and run on Galileo Gen2
Change-Id: I667b9bc5fcde7f68cb9b4c8fa85601998e5c81ff
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14870
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit d3989a26c1)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346524
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Coverity does not like the use of for/break, switch to using returns
instead.
Found-by: Coverity CID 1349855
TEST=Build and run on Galileo Gen2
Change-Id: I4e5767b09faefa275dd32d3b76dda063f7c22f6f
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14869
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 00c35c1a98)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346523
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Add Ioh.h from EDK-II to enable easy comparisons between EDK-II and
coreboot implementations.
TEST=Build and run on Galileo Gen2
Change-Id: I9320101a4a2c16ed18f682f3d04623c54afb52fd
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14824
Original-Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
(cherry-picked from commit c1cbc605cd)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346522
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Don't allow an array index of 2 to be processed by the code referencing
the array.
Found-by: Coverity CID 1353337
TEST=None
Change-Id: I586ca14416a6e40971f8f6f4066fbdb4908ca688
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14868
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry-picked from commit 016d8f75d8)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346521
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Using a dedicated variable is slightly less readable and makes the code
less consistent, given that other test functions are called directly in
the if statements.
Change-Id: If52b2a4268acb1e2187574d15cc73a0c1d5fe9bb
Original-Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Original-Reviewed-on: https://review.coreboot.org/14817
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry-picked from commit 1811768c64)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346519
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Add helper functions for generating some common objects:
acpigen_write_STA(status) will generate a status method that will
indicate the device status as provided:
Method (_STA) { Return (status) }
Full status byte configuration is possible and macros are provided for
the common status bytes used for generated code:
ACPI_STATUS_DEVICE_ALL_OFF = 0x0
ACPI_STATUS_DEVICE_ALL_ON = 0xF
acpigen_write_PRW() will generate a Power Resoruce for Wake that describes
the GPE that will wake a particular device:
Name (_PRW, Package (2) { wake, level }
Change-Id: I10277f0f3820d272d3975abf34b9a8de577782e5
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/14795
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry-picked from commit abe2de8854)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346518
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
In order to produce smaller AML and not rely on the caller to size the
output type appropriately add a helper function that will output an
appropriately sized integer.
To complete this also add helper functions for outputting the single
OpCode for Zero and One and Ones.
And finally add "name" variants of the helpers that will output a
complete sequence like "Name (_UID, Zero)".
Change-Id: I7ee4bc0a6347d15b8d49df357845a8bc2e517407
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/14794
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
(cherry-picked from commit f7c3876c28)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346517
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Add helper function to emit a string into the SSDT AML bytestream with a
NULL terminator. Also add a helper function to emit the string OpCode
followed by the string itself.
acpigen_emit_string(string) /* Raw string output */
acpigen_write_string(string) /* OpCode followed by raw string */
Change-Id: I4a3a8728066e0c41d7ad6429fad983e6ae6962fe
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/14793
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry-picked from commit 56b69aa9c7)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346516
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Add helpers for writing word and dword values in acpigen and use them
throughout the file to clean things up:
acpigen_emit_word - write raw word
acpigen_emit_dword - write raw dword
acpigen_write_word - write word opcode and value
Change-Id: Ia758d4dd25d0ae5b31be7d51b33866dddd96a473
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/14792
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
(cherry-picked from commit 9ccae7558d)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346515
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Add support for a basic generic device in the devicetree to bind to a
device that does not have a specific bus, but may need to be described
in tables for the operating system. For instance some chips may have
various GPIO connections that need described but do not fall under any
other device.
In order to support this export the basic 'scan_static_bus()' that can
be used in a device_operations->scan_bus() method to scan for the generic
devices.
It has been possible to get a semi-generic device by using a fake PNP
device, but that isn't really appropriate for many devices.
Also Re-generate the shipped files for sconfig. Use flex 2.6.0 to avoid
everything being rewritten. Clean up the local paths that leak into the
generated configs.
Change-Id: If45a5b18825bdb2cf1e4ba4297ee426cbd1678e3
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/14789
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
(cherry-picked from commit 4650f5baff)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346514
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Use the second token for an i2c device entry in devicetree.cb to
indicate if it should use 10-bit addressing or 7-bit. The default if
not provided is to use 7-bit addressing, but it can be changed to
10-bit addressing with the .1 suffix. For example:
chip drivers/i2c/generic
device i2c 3a.1 on end
end
Change-Id: I1d81a7e154fbc040def4d99ad07966fac242a472
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/14788
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry-picked from commit b7ce5fe311)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346513
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Currently you cannot assign a string to a register in devicetree because
the quotes are removed when parsing and the literal is assigned directly.
Add a parse option for two double-quotation marks to indicate a string
and return a quoted literal that can be assigned to a register with a
'const char *' type.
Example:
chip drivers/i2c/generic
register hid = INT343B
register uid = 1
device i2c 15 on end
end
Change-Id: I621cde1f7547494a8035fbbab771f29522da1687
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/14787
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry-picked from commit b1fb0152bf)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346512
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Long options can be useful when writing examples and documentation
as they are more expressive and obvious to the reader.
Change-Id: I39496765ba1f15ccc2ffe1ad730f0f95702f82b8
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/14736
Original-Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
(cherry-picked from commit b2aa5283e6)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346511
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
This adds the initial scaffolding for the reef reference board.
One big thing missing is the GPIO configuration.
Change-Id: I8e2d275df296bb397bb33dbd0c66fc87c82ff10f
Original-Signed-off-by: Aaron Durbni <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/14798
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Original-Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
(cherry-picked from commit e065bb43d7)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346510
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
