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UPSTREAM: soc/intel/apollolake: Work around FSP-M CAR layout

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As of now FSP-M can not be relocated and it can not be instructed
to use a specific resource for temporary memory. As result coreboot
is forced to use CAR layout dictated by default FSP-M configuration.

Change CAR size to 1MiB, link romstage at such CAR address so it
doesn't overlap with FSP-M's default heap/stack.

Change-Id: I56f78f043099dc835e294dbc081d7506bfad280d
Original-Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14804
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
(cherry-picked from commit 0e46307574)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346623
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Andrey Petrov 2016-04-23 14:28:21 -07:00 • committed by chrome-bot
commit 243b7eb07c
1 changed files with 2 additions and 2 deletions
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4
src/soc/intel/apollolake/Kconfig
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@ -73,7 +73,7 @@ config DCACHE_RAM_BASE
config DCACHE_RAM_SIZE
hex "Length in bytes of cache-as-RAM"
default 0x80000
default 0x100000
help
The size of the cache-as-ram region required during bootblock
and/or romstage.
@ -116,7 +116,7 @@ config X86_TOP4G_BOOTMEDIA_MAP
config ROMSTAGE_ADDR
hex
default 0xfef2e000
default 0xfef3e000
help
The base address (in CAR) where romstage should be linked