Fix the board ID handling.
Recovery switch and WP status GPIO has been reassigned in board rev3.
Configure related GPIOs based on Board ID.
BUG=chrome-os-partner:55320
TEST=Verified GPIO assignment for Rev.1 board.
BRANCH=None
Change-Id: I6d3d5df2e9017f7845edc3cd0b2c19ad7c58a97c
Signed-off-by: Kan Yan <kyan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/361393
Reviewed-by: David Hendricks <dhendrix@chromium.org>
At first boot CSE spends long time preparing media for use. As result
it may not be able to deal with a CPU reset. Add reset_prepare()
callback that polls CSE readiness.
BUG=chrome-os-partner:55055
BRANCH=None
TEST=build with release version of fsp, reboot, observe polling for
CSE, then proper reboot happening
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15721
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I639ef900b97132f1a7f269bb864d70009df9fdfe
Reviewed-on: https://chromium-review.googlesource.com/361784
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These are issues that were found by the updated toolchain at
coreboot.org:
* mode_sel was possibly being used before being initialized, so
initialize it. Note that this can't actually happen after adding the
halt for the unknown DRAM type, but the compiler still complained.
* vref_mode and speed were possibly being used without being
initialized, so halt if they don't get initialized. Note that this
change was pushed to coreboot.org before the latest refactoring,
and it looks like speed isn't being used at all now. I'll remove
that in a follow-on change.
BRANCH=none
BUG=none
TEST=none
Change-Id: I3f25e7980f1b0620517f25667ac744f4c9edc4b3
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361363
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These are some minor changes that were made at coreboot.org
as patches were pulled in.
* Fix grammar and spelling in comments
* Change setup (noun) to set up (verb)
* Change workaround (noun) to work around (verb)
* Capitalize EDID and Rockchip.
* Add whitespace around * operators
* Add period at the end of a sentence in a comment
BRANCH=none
BUG=none
TEST=none
Change-Id: Ic23e4255e51e9181b6139cba31ae5bdbff518569
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361362
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These are some minor changes that were made at coreboot.org
as patches were pulled in.
* Add whitespace around comments
* Remove trailing whitespace from text
* Update error text for grammar
BRANCH=none
BUG=none
TEST=none
Change-Id: Ic72b1577de80010f538dfe6ee8ffefffde8cfd23
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361361
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The FSPS component loading was just loading to any memory address
listed in the header. That could be anywhere in the address space
including ramstage itself -- let alone corrupting the OS memory on
S3 resume. Remedy this by loading and relocating FSPS into cbmem.
The UEFI 2.4 header files include path are selected to provide the
types necessary for FSP relocation.
BUG=chrome-os-partner:52679
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15742
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: John Zhao <john.zhao@intel.com>
Change-Id: Iaba103190731fc229566a3b0231cf967522040db
Reviewed-on: https://chromium-review.googlesource.com/361775
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: John Zhao <john.zhao@intel.com>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: John Zhao <john.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The previously implementation for loading the FSPM component didn't
handle platforms which expects FSPM to be XIP. For the non-XIP case,
romstage's address space wasn't fully being checked for overlaps.
Lastly, fixup the API as the range_entry isn't needed any longer.
This API change requires a apollolake to be updated as well.
BUG=chrome-os-partner:52679
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15741
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: I24d0c7d123d12f15a8477e1025bf0901e2d702e7
Reviewed-on: https://chromium-review.googlesource.com/361774
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of performing the same tasks in the chipset code move
the common sequences into the FSP 2.0 driver. This handles the
S3 paths as well as saving and restoring the memory data. The
chipset code can always override the settings if needed.
BUG=chrome-os-partner:52679
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15739
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: I098bf95139a0360f028a50aa50d16d264bede386
Reviewed-on: https://chromium-review.googlesource.com/361772
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The amount of reserved memory just below the DRAM limit in
32-bit space is defined in the FSP 2.0 specification within
the FSPM_ARCH_UPD structure. There's no need to make the
chipset code set the same value as needed for coreboot.
The chipset code can always change the value if it needs
after the common setting being applied.
Remove the call in soc/intel/apollolake as it's no longer
needed.
BUG=chrome-os-partner:52679
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15738
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Change-Id: I69a1fee7a7b53c109afd8ee0f03cb8506584d571
Reviewed-on: https://chromium-review.googlesource.com/361771
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We set this driving control to prevent signal attenuation caused by
LVDS DRV termination.
When DA_LVDSTX_PWR_ON is not set, LVSH has no power and LVDS DRV
termination status is unknown(floating). And there is a chance that MIPI
output would be influence. The DSI's LP signal will be half voltage
attenuation. There will be no display on panel.
When DA_LVDSTX_PWR_ON is set, LVSH and LVDS DRV termination would be
effective and termination is fixed OFF. The DSI won't be influence.
We only need to set this register once. So we set it here to prevent
repeat setting in the kernel when the system goes to recovery mode.
BUG=chrome-os-partner:55296
BRANCH=none
TEST=build pass elm and show ui
Change-Id: Ie71f9cc41924787be8539c576392034320b57a49
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/360850
Commit-Ready: jitao shi <jitao.shi@mediatek.com>
Tested-by: jitao shi <jitao.shi@mediatek.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Since the Integrated Sensor Hub can be disabled through devicetree.cb
as a PCI device, there is no need for a separate register variable.
Remove handling the register and update mainboards' devicetrees. Also
keep ISH disabled on both Reef and Amenia.
Change-Id: I90dbf57b353ae1b80295ecf39877b10ed21de146
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15710
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/361219
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
1. The hotplug feature needs to be disabled
so that pcie root ports will be disabled by fsp
2. Correct PcieRootPortEn mapping.
The correct mapping should be like below
PcieRootPortEn[0] ==> 00:14.0
PcieRootPortEn[1] ==> 00:14.1
PcieRootPortEn[2] ==> 00:13.0
PcieRootPortEn[3] ==> 00:13.1
PcieRootPortEn[4] ==> 00:13.2
PcieRootPortEn[5] ==> 00:13.3
BUG=chrome-os-partner:54288
BRANCH=None
TEST=Checked pcie root port is disabled properly
and make sure pcie ports are coalesced.
Also make sure the device will still be enabled after coalescence
when pcie on function 0 is disabled devicetree
Change-Id: I39c482a0c068ddc2cc573499480c3fe6a52dd5eb
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/15595
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361218
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The ramstage main() in lib/hardwaremain.c has the logic
to set the ACPI sleep state based on romstage_handoff. Thus,
there's no need to do it a second time.
BUG=None
BRANCH=None
TEST=None
Change-Id: I75172083587c8d4457c1466edb88d400f7ef2dd0
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/15662
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360821
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The ramstage main() in lib/hardwaremain.c has the logic
to set the ACPI sleep state based on romstage_handoff. Thus,
there's no need to do it a second time.
BUG=None
BRANCH=None
TEST=None
Change-Id: I88af301024fd6f868f494a737d2cce14d85f8241
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/15661
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360820
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
CBMEM should be placed at the top of RAM, which can be found by parsing
the configuration string. Configuration string parsing isn't yet
implemented, so I'll hard-code the CBMEM location for now.
BUG=None
BRANCH=None
TEST=None
Change-Id: If4092d094a856f6783887c062d6682dd13a73b8f
Original-Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Original-Reviewed-on: https://review.coreboot.org/15284
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360819
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
It is not used in this file.
BUG=None
BRANCH=None
TEST=None
Change-Id: I59bb41370b97b79073c0fd82b1dbcae9fd8a62d0
Original-Reported-by: GCC 6.1.0
Original-Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Original-Reviewed-on: https://review.coreboot.org/15552
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360814
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
There is currently a SMBus driver implemented for soc/intel/broadwell
which nearly matches Broadwell-DE as well. Use this driver as template
and add minor modifications to make it work for Broadwell-DE. Support in
romstage is not available and can be added with a different patch.
BUG=None
BRANCH=None
TEST=None
Change-Id: I64649ceaa298994ee36018f5b2b0f5d49cf7ffd0
Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/15617
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360808
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This patch adds the support for gpio_tier1_sci_en bit which
needs to be set before going to sleep so that when
gpio_tier1_sci_sts bit gets set platform can wake
from S3.
BUG = chrome-os-partner:53992
TEST = Platform wakes from S3 on lidopen,key press.
Tested on Amenia and Reef boards.
Change-Id: I3ba79fa53ca8817149d585fa795a8f427c128dcb
Original-Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15612
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360801
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
FSP is currently setting a hard-coded policy for the interrupt
polarity settings. When the mainboard has already set the GPIO
settings up prior to SiliconInit being called that results
in the previous settings being dropped. Work around FSP's
default policy until FSP is fixed.
BUG=chrome-os-partner:54955
Change-Id: Ibbd8c4894d8fbce479aeb73aa775b67df15dae85
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/15649
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360800
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
For APIC routed gpios, set the corresponding interrupt polarity
for the associated IRQ based on the gpio pad's invert setting.
This allows for the APIC redirection entries to match the hardware
active polarity once the double inversion takes place to meet
apollolake interrupt triggering constraints.
BUG=chrome-os-partner:54955
Change-Id: I69c395b6f861946d4774a4206cf8f5f721c6f5f4
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/15648
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360729
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The interrupt and timer subsystem (ITSS) sits between the APIC
and the other logic blocks. It only supports positive polarity
events, but there's a polarity inversion setting for each IRQ such
that it can pass the signal on to the APIC according to the
expected APIC redirection entry values. This support is needed
in order for the platform/board to set the expected interrupt
polarity into the APIC for gpio signals.
BUG=chrome-os-partner:54955
Change-Id: I50ea1b7c4a7601e760878af515518cc0e808c0d1
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/15647
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360728
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Internally, apollolake routes its interrupts as active high.
This includes SCI, SMI, and ACPI. Therefore, provide helper
macros such that the user can describe an interrupt's active
high/low polarity more easily. It helps for readability when
one is comparing gpio configuration next to APIC configuration
in different files. Additionally, the gpio APIC macros always
use a LEVEL trigger in order to let the APIC handle the
filtering of the IRQ on its own end.
BUG=chrome-os-partner:54977
BUG=None
BRANCH=None
TEST=None
Change-Id: Id8fdcd98f0920936cd2b1a687fd8fa07bce9a614
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/15644
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360725
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Asserting this GPIO will send a signal to the EC to trigger a reset
for the AP and the CR50.
BRANCH=none
BUG=chrome-os-partner:55252
TEST=the device now reboots when it needs to switch between different
boot modes instead of hanging with "failed to reboot" message.
Change-Id: Idfd20977cf3682bd8933f89e8eec53005e55864e
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360238
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch adds the handler to enable bit for gpio_tier1_sci_en.
gpio_tier1_sci_en enables the setting of the GPIO_TIER1_SCI_STS
bit to generate a wake event and/or an SCI or SMI#. We are setting
the bit for gpio_tier1_sci_en from the ASL code as OS clears this bit
if set from BIOS. As per ACPI spec _GPE is defined as the Named
Object that evaluates to either an integer or a package. If _GPE
evaluates to an integer, the value is the bit assignment of the SCI
interrupt within the GPEx_STS register of a GPE block described in
the FADT that the embedded controller will trigger. FADT right now
has no mechanism to acheive the same.
Change-Id: I1e1bd3f5c89a5e6bea2d1858569a9d30e6da78fe
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15578
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360203
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Properly obtain the top of memory address from the hardware registers
set by FSP.
TEST=Build and run on Galileo Gen2
Change-Id: I7681d32112408b8358b4dad67f8d69581c7dde2e
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15594
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/360200
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
rk3399 sdram size is 192K, there still some space do not use now,
we need more romstage space to include sdram config, so extend
romstage range.
BRANCH=none
BUG=chrome-os-partner:54871
TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass
Change-Id: Ib5aa1e1b942cde8d9476773f5a84ac70bb830c80
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/359092
Reviewed-by: Julius Werner <jwerner@chromium.org>
kevin rev3 pwm regulator ripple still not great, especially for
center logic, for supporting sdram 800MHz stable, raise up it to
0.95v.
BRANCH=none
BUG=chrome-os-partner:54871
TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass
Change-Id: Ideec9c3ab2f919af732719ed2f6a702068d99c8f
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/359130
Commit-Ready: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This removes an empty function for sdram training. If it's needed
later, we can always add it back.
BRANCH=none
BUG=none
TEST=build and boot firmware for kevin/gru
Change-Id: I6bf77d2f81719c68cd78722c3fe9ae547ea1e79c
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354164
Reviewed-by: Martin Roth <martinroth@chromium.org>
This changes the src arg for copy_to_reg to a const u32 * instead of a
u32 * in sdram.c.
BRANCH=none
BUG=none
TEST=emerge-gru coreboot
Change-Id: I362727f1dbe6726bf3240f9219c394786162a1a0
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354163
Reviewed-by: Martin Roth <martinroth@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This simplifies some of the code with better variable declaractions
which removes a lot of line continuations. Instead of declaring a
pointer to the container of the needed struct or array, this retrieves
a pointer to the struct or array instead.
BRANCH=none
BUG=none
TEST=check that gru and kevin still build and boot properly followed
by running "stressapptest -M 1024 -s 1000" and making sure it passes
Change-Id: If4e386d4029f17d811fa3ce83e5be89e661a7b11
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354162
Reviewed-by: Martin Roth <martinroth@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
This removes a variable that was only used once and makes variable
declarations consistent by moving those only used in one block of code
into that block.
BRANCH=none
BUG=none
TEST=on kevin/gru, run "stressapptest -M 1024 -s 3600"
Change-Id: Id0ff0c45189c292ab40e1c4aa27929fb7780e864
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/355667
Reviewed-by: Martin Roth <martinroth@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
