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UPSTREAM: rockchip: update whitespace and text

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These are some minor changes that were made at coreboot.org
as patches were pulled in.

* Fix grammar and spelling in comments
* Change setup (noun) to set up (verb)
* Change workaround (noun) to work around (verb)
* Capitalize EDID and Rockchip.
* Add whitespace around * operators
* Add period at the end of a sentence in a comment

BRANCH=none
BUG=none
TEST=none

Change-Id: Ic23e4255e51e9181b6139cba31ae5bdbff518569
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361362
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Martin Roth 2016-07-18 10:43:01 -06:00 • committed by chrome-bot
commit bd0f3d20d5
6 changed files with 15 additions and 15 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/soc/rockchip/common/include/soc/gpio.h
View file

@ -79,7 +79,7 @@ enum {
PULLDOWN
};
/* The gpio pull bias setting may different from SoC */
/* The gpio pull bias setting may be different between SoCs */
u32 gpio_get_pull_val(gpio_t gpio, u32 pull);
#endif

10
src/soc/rockchip/rk3399/display.c
View file

@ -57,7 +57,7 @@ void rk_display_init(device_t dev, uintptr_t lcdbase,
case VOP_MODE_AUTO_DETECT:
/* try EDP first, then HDMI */
case VOP_MODE_EDP:
printk(BIOS_DEBUG, "Attempting to setup EDP display.\n");
printk(BIOS_DEBUG, "Attempting to set up EDP display.\n");
rkclk_configure_vop_aclk(conf->vop_id, 192 * MHz);
/* select edp signal from vop0(big) or vop1(little) */
@ -65,8 +65,8 @@ void rk_display_init(device_t dev, uintptr_t lcdbase,
RK_CLRBITS(1 << 5);
write32(&rk3399_grf->soc_con20, val);
/* select edp clk from SoC interal 24M crystal, otherwise,
* it will source from edp's 24M clock(that depends on
/* select edp clk from SoC internal 24M crystal, otherwise,
* it will source from edp's 24M clock (that depends on
* edp vendor, could be unstable)
*/
write32(&rk3399_grf->soc_con25, RK_SETBITS(1 << 11));
@ -85,7 +85,7 @@ void rk_display_init(device_t dev, uintptr_t lcdbase,
printk(BIOS_WARNING, "HDMI display is NOT supported yet.\n");
return;
default:
printk(BIOS_WARNING, "Cannot read any edid info, aborting.\n");
printk(BIOS_WARNING, "Cannot read any EDID info, aborting.\n");
return;
}
@ -111,7 +111,7 @@ void rk_display_init(device_t dev, uintptr_t lcdbase,
case VOP_MODE_EDP:
default:
if (rk_edp_enable()) {
printk(BIOS_WARNING, "edp enable err\n");
printk(BIOS_WARNING, "edp enable error\n");
return;
}
mainboard_power_on_backlight();

4
src/soc/rockchip/rk3399/include/soc/addressmap.h
View file

@ -61,8 +61,8 @@
#define RK_PWM_BASE 0xff420000
#define EDP_BASE 0xff970000
#define VOP_BIG_BASE 0xff900000 /* corresponsed to vop_id 0 */
#define VOP_LIT_BASE 0xff8f0000 /* corresponsed to vop_id 1 */
#define VOP_BIG_BASE 0xff900000 /* corresponds to vop_id 0 */
#define VOP_LIT_BASE 0xff8f0000 /* corresponds to vop_id 1 */
#define DDRC0_BASE_ADDR 0xffa80000

2
src/soc/rockchip/rk3399/romstage.c
View file

@ -49,7 +49,7 @@ static void init_dvs_outputs(void)
write32(&rk3399_pmugrf->iomux_pwm_3a, IOMUX_PWM_3_A); /* Centerlog */
/*
* Setup voltages for all DVS rails.
* Set up voltages for all DVS rails.
*
* LITTLE CPU: At the speed we're running at right now and on the
* early silicon, .9V is sane. If/when we run faster, let's bump this.

10
src/soc/rockchip/rk3399/sdram.c
View file

@ -361,11 +361,11 @@ static void phy_io_config(u32 channel,
/* PHY_939 PHY_PAD_CS_DRIVE */
clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
if (sdram_params->ddr_freq < 400*MHz)
if (sdram_params->ddr_freq < 400 * MHz)
speed = 0x0;
else if (sdram_params->ddr_freq < 800*MHz)
else if (sdram_params->ddr_freq < 800 * MHz)
speed = 0x1;
else if (sdram_params->ddr_freq < 1200*MHz)
else if (sdram_params->ddr_freq < 1200 * MHz)
speed = 0x2;
/* PHY_924 PHY_PAD_FDBK_DRIVE */
@ -398,7 +398,7 @@ static void pctl_cfg(u32 channel,
u32 pwrup_srefresh_exit;
/*
* workaround controller bug:
* work around controller bug:
* Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed
*/
copy_to_reg(&denali_ctl[1], &params_ctl[1],
@ -506,7 +506,7 @@ static void select_per_cs_training_index(u32 channel, u32 rank)
* "0x200-PHY_CLK_WRDQS_SLAVE_DELAY < 0x20 or
* 0x200-PHY_CLK_WRDQS_SLAVE > 0x1E0",
* enable PHY_WRLVL_EARLY_FORCE_ZERO for this slice, and trigger write
* leveling again. Else no additional write leveling is required
* leveling again. Else no additional write leveling is required.
*/
static void check_write_leveling_value(u32 channel,
const struct rk3399_sdram_params

2
src/soc/rockchip/rk3399/usb.c
View file

@ -67,7 +67,7 @@ static void setup_dwc3(struct rockchip_usb_drd_dwc3 *dwc3_reg)
DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST));
/*
* Configure USB phy interface of DWC3 core.
* For rockchip rk3399 SOC DWC3 core:
* For Rockchip rk3399 SOC DWC3 core:
* 1. Clear U2_FREECLK_EXITS.
* 2. Select UTMI+ PHY with 16-bit interface.
* 3. Set USBTRDTIM to the corresponding value