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UPSTREAM: rockchip/rk3399: fix compiler warnings from coreboot.org

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These are issues that were found by the updated toolchain at
coreboot.org:
* mode_sel was possibly being used before being initialized, so
initialize it. Note that this can't actually happen after adding the
halt for the unknown DRAM type, but the compiler still complained.
* vref_mode and speed were possibly being used without being
initialized, so halt if they don't get initialized. Note that this
change was pushed to coreboot.org before the latest refactoring,
and it looks like speed isn't being used at all now.  I'll remove
that in a follow-on change.

BRANCH=none
BUG=none
TEST=none

Change-Id: I3f25e7980f1b0620517f25667ac744f4c9edc4b3
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361363
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Martin Roth 2016-07-18 10:52:59 -06:00 • committed by chrome-bot
commit f0e340eb0f
1 changed files with 5 additions and 1 deletions
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6
src/soc/rockchip/rk3399/sdram.c
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@ -312,7 +312,7 @@ static void phy_io_config(u32 channel,
{
u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy;
u32 vref_mode, vref_value;
u32 mode_sel;
u32 mode_sel = 0;
u32 speed;
u32 reg_value;
@ -323,6 +323,8 @@ static void phy_io_config(u32 channel,
vref_mode = 0x2;
else if (sdram_params->dramtype == DDR3)
vref_mode = 0x1;
else
die("Halting: Unknown DRAM type.\n");
vref_value = 0x1f;
reg_value = (vref_mode << 9) | (0x1 << 8) | vref_value;
@ -367,6 +369,8 @@ static void phy_io_config(u32 channel,
speed = 0x1;
else if (sdram_params->ddr_freq < 1200 * MHz)
speed = 0x2;
else
die("Halting: Unknown DRAM speed.\n");
/* PHY_924 PHY_PAD_FDBK_DRIVE */
clrsetbits_le32(&denali_phy[924], 0x3 << 21, mode_sel << 21);