8d4f36f436
The interrupt and timer subsystem (ITSS) sits between the APIC and the other logic blocks. It only supports positive polarity events, but there's a polarity inversion setting for each IRQ such that it can pass the signal on to the APIC according to the expected APIC redirection entry values. This support is needed in order for the platform/board to set the expected interrupt polarity into the APIC for gpio signals. BUG=chrome-os-partner:54955 Change-Id: I50ea1b7c4a7601e760878af515518cc0e808c0d1 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://review.coreboot.org/15647 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Original-Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/360728 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> |
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| broadcom/cygnus | ||
| dmp/vortex86ex | ||
| imgtec/pistachio | ||
| intel | ||
| marvell | ||
| mediatek/mt8173 | ||
| nvidia | ||
| qualcomm | ||
| rdc/r8610 | ||
| rockchip | ||
| samsung | ||
| ucb/riscv | ||