SlowSlewRate, AcousticNoiseMitigation and FastPkgCRampDisable upds
can be overwritten with this patch.
BUG=none
TEST=Able to override the acoustic noise UPDs.
Change-Id: I5bfa98834f8d7cfcaab3fdbb7dde914d78529581
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Kelsier shares the same firmware with Kaladin so coreboot loads the same
loader firmware to ISH. Since Kelsier is a sensor-less design, change
it to load lite_ish.bin and disable ISH related GPIOs depending on
firmware config.
BUG=b:441613379
TEST=flash and boot to DUT, check suspend function works normally on
kelsier
Change-Id: I04c77db813fcd993217b5c366872cc583e265939
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Add mapping of different SKUs based on CPU ID and TDP values.
Add PowerLimits (PL) values.
Add i_trip value for Fast Vmode.
Note: The i_trip value, the value at which the Voltage Regulator (VR)
or SoC will trigger a protective action such as throttling or
entering Fast Vmode is, due to not being documented, currently set at
70% of the maximum current the VR is designed to support for a rail.
The actual i_trip value to be updated once it is available.
Ref=858124 Power Delivery Guide Rev1p0
830097 Powermap Rev1p1
BUG=b:433211504
TEST= Build Ocelot and verify it compiles without any error.
check CPU log for the following error
[ERROR] Could not find the SKU power map
With the current patch this error line is not seen in the CPU log
anymore.
Change-Id: I8c54efc8eb360ed6f814a336448bb204d5ab0268
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88858
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
As per Intel document 853127, EPD_ON_GCD_OUT (previously GPP_A15)
is no longer available for other functions. Updated GPIO
configuration accordingly.
Reference: Intel doc 853127
BUG=none
TEST=Build and boot test on fatcat hardware
Change-Id: Ie4a3967ceecd10905ba0424d85d8f1392625bf16
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89103
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the matsu variant of the ocelot reference board by copying
the ocelot files to a new directory named for the variant.
BUG=b:443612246
TEST=1. util/abuild/abuild -p none -t google/ocelot -x -a
make sure the build includes GOOGLE_MATSU
2. Run part_id_gen tool without any errors
Change-Id: I81d010fdda927db56d7b41ddc527c1c40b2cf768
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Update GPIO_PCH_WP configuration for trulo varaints as the value
in the baseboard is changed.
BUG=b:443677716, b:435612546
TEST=Build uldrenite, pujjocento and orisa firmware successfully
Change-Id: I7fb35091000b1df1b8008f26488e9290be3efe2d
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Change GPIO_PCH_WP from GPP_E3 to GPP_E12 to align with trulo
reference hardware schematic.
BUG=b:443677716, b:435612546
TEST=Build pujjolo and kaladin firmware and verify SPI ROM
write-protect
Change-Id: I935d74cb5447f45f297fe45506c14623095d7127
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89117
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change stylus gpio and wake source setting to let eventlog could
show GPE #12 message when interrupt suspend by stylus.
BUG=b:439761057
TEST=Build and boot to OS, do the suspend_stress_test and check
eventlog show wake source information. And do warmboot/coldboot/
suspend 500 times stress test all pass.
Change-Id: I8d16e867fd56f1072b09bb6ab71b6d08a7d38376
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89129
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
Uldrenite14 need to set this config since we use unified firmware
for UFS and eMMC skus.
BUG=b:437006063
TEST=emerge-nissa coreboot
Change-Id: I86f41a4e6c9c136f031eb3813efa3c06043237b9
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88932
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds a wake configuration to the cnvi_bluetooth device for
all the ptlrvp board variants. The "wake" setting is now registered to
"GPE0_PME_B0" using the common CNVi block. This enhancement ensures that
the cnvi_bluetooth device can properly wake the system.
TEST=Able to wake up the device from a low power state using a keyboard
Bluetooth device.
Change-Id: I4c17ca926a4409cedfaef24a802330ef463703ac
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
This commit introduces a new configuration structure for the
Connectivity Integration (CNVi) block in Intel SoCs.
The added soc_intel_common_block_cnvi_config structure, located in
chip.h, defines a wake pin that specifies the ACPI Power Resources for
Wake (_PRW), enabling wake-up capabilities from sleep states.
This enhancement provides a structured way to handle CNVi
configurations, which is crucial for managing device power states and
ensuring proper wake functionalities as defined by ACPI standards.
Change-Id: Ide6dea04cb089d73fe6aad9fb91044f9eb43edc6
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
The QT based xconfig util is broken for several reasons.
1. On systems with qt6 (which is a majority on modern distros),
the qconf-cfg.sh script appends a c++17 flag to the output file,
which makes the value of $(HOSTCXXFLAGS_qconf.o) - a multiline string.
This causes problem during compiler invocation, thus we can observe:
'g++: fatal error: no input files'
Flattening the HOSTCXXFLAGS_ with $strip function resolves the problem
2. The missing Qt's Meta-Object file "qconf-moc.cc",
which should be autogenerated during build by invoking "moc" tool.
The current set of recipes in Makefile.mk aren't triggering
the moc generation. Explicitly adding "qconf-moc.o" target,
with dependency on "qconf-moc.cc" resolves the problem.
3. "$(call if_changed,moc)" used to invoke "moc" tool isn't working,
due to missing "if_changed" macro.
Replace it with direct call to "cmd_moc" in "Makefile.real".
Bringing the full implementation of "if_changed" seem to be impractical,
as it uses too many dependent functions and macros.
BUG=https://ticket.coreboot.org/issues/518
Change-Id: I7eb1e71aeb6a92b8d3c194a369bd3bd6dc708863
Signed-off-by: Dmytro Aleksandrov <alkersan@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89006
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
During the ACPI initialization phase at boot, the driver
is pulled, causing the LED of the WFC camera flash.
This issue can be resolved by replacing GPP_D15 with
GPP_D16 in the mipi settings.
BUG=b:434106137
TEST= Build and boot to OS, and check the Chromebook
logo will not flash
Change-Id: I2fce7f7c9c5c852efbdef3e5ef757cab3433f4c6
Signed-off-by: erin liang <erin.liang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89014
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the new memory support: Hynix H58G56CK8BX146
BUG=b:444335746
BRANCH=firmware-brya-14505.B
TEST=Run part_id_gen tool and check the generated files.
Change-Id: Id473adafffc1dabcb8f8e9a1f548966a0ba5a334
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89147
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds the necessary configuration for the parade
touchscreen (PRT3406) device, connected to I2C bus 24.
It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset, stop and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset
BUG=b:431660019
TEST=emerge-nissa coreboot and parade touchscreen can work well
Change-Id: Iaaf740032de973461b616e186ac628436cbbc2a5
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
BUG=b:440996061
TEST=Ensure that pipe/utmi clocks are ON and check
port link status to confirm USB connect.
Change-Id: If0997ecb43eb5f687f1416abe42764fa31b1eaf5
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add support for HS-PHY/SS-PHY and DWC3 USB controllers
for USB Type A Host support.
TEST = Ensure that pipe/utmi clocks are ON and check
port link status to confirm USB connect.
Change-Id: Ife08801062da5a8f87491b020b3828c246aadea8
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89132
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the memory parts: H58G66CK8BX147 (Hynix) in mem_parts_used.txt
,and generate SPD id for the parts.
BUG=none
TEST=Run part_id_gen tool and check the generated files.
Change-Id: I485d8f947b6d8efc5b43ea1ddf1e4187eb4cf2bb
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit adds support for logging Bluetooth device wake events in the
Pantherlake platform. It improves visibility into wake events triggered
by Bluetooth devices, which is crucial for debugging and power
management analysis.
Change-Id: I36bb08075e79ab3151cfdaf41ace2121aaac0973
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89057
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces a new constant, ELOG_WAKE_SOURCE_PME_BLUETOOTH,
with the value 0x31 to represent Bluetooth as a wake source in the ELOG
event data structure. This change facilitates diagnostics and
event logging related to Bluetooth activity.
The cbfstool eventlog has been updated to include "PME - BLUETOOTH" in
the wake source types for event data printing.
Change-Id: Ib628502ddcccb4a781394a39b2aee6efa05ecf84
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
The header guard comment in the chip.h file was incorrect, using
_GENERIC_WIFI_H_ instead of the correct _WIFI_GENERIC_H_. This
commit corrects the typo to ensure consistency.
Change-Id: I00a93e811608ddf449065bc92441648f7332fc4b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89055
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Add support for USB controller, PHY and NOC clocks.
The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
TEST=Verify the boot process on the X1P42100 by creating an
image.serial.bin. After booting, confirm that the USB clocks are
on by inspecting the Clock Branch Control Register (CBCR) for
each clock. The status is indicated by BIT31, where a low value
means the clock is on.
Change-Id: Ic78e75c2c9963311530172d802aabb03f540060c
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
When CONFIG_SSE is enabled use the "prefetchnta" instruction to load
the next chunk of data into the CPU cache. This only works when the
input stream is covered by an MTRR. In case the input stream is read
from the SPI ROM MMIO area it allows to keep the SPI controller
busy fetching new data, which is automatically placed into the CPU
cache, resulting in less I/O wait on the CPU side and faster
decompression.
When the input stream is not cachable the prefetch instruction has no
effect.
The SPI interfaces on the tested device runs at 100Mbit/s and the
Sandy Bridge mobile CPU has quite some work to do decompressing the
LZMA stream.
That gives the SPI controller enough time to preload data into the
cache.
The payload of 1100213 bytes is now read in 164msec, resulting in an
input bandwidth of 53MBit/s.
TEST=Booted on Lenovo X220 and used cbmem -t:
Before:
16:finished LZMA decompress (ignore for x86) 1,218,418 (210,054)
After:
16:finished LZMA decompress (ignore for x86) 1,170,949 (164,868)
Boots 46msec faster than before or 30% faster than before.
Change-Id: I3b2ed7fe0883f271553ecd1ab4191e4848ad0299
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Reorder Child Device mappings to prioritise EFP displays.
* Disable LFP1 as it is not present
Change-Id: Ib998bc6df5430d08f9ded4d1e84f5aaa57b8be3d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89097
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Reorder Child Device mappings to prioritise EFP displays.
* Disable EFP3 as it is not present
* Change eDP panel colour depth from 18-bit to 24-bit (8 bpc).
* Change POST brightness from 255 to 100.
* Change minimum brightness from 6 to 0.
* Change DPST aggresiveness to 6 to 2.
* Enable PSR
Change-Id: I895fc61dff120e0ae989f45b37c0c5cde3c5e2ce
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89095
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implements clock-based reset control via CLK_CTL_ARES_SHFT bit
in CBC, enabling reset of cores receiving CBC-generated clocks.
This is required for proper initialization of clocks needed for
subsystems like USB Type-A.
TEST: Verified on x1p42100 CRD by asserting CLK_ARES through CBC
register writes during USB Type-A enablement. Confirmed USB
enumeration and reset functionality serial console.
Change-Id: If878994eaa24a21061470f962a4883f29be5476f
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
:wq
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89102
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tracker is a debugging tool, including AP/INFRA tracker. When bus
timeout occurs, the system reboots and latches some values which could
be used for debug. On MT8189, this feature is enabled by using the
common driver tracker_v3.
BUG=b:379008996
BRANCH=skywalker
TEST=When detected bus timeout, tracker show:
**Dump systracker aw debug register start**
0x10208ae0:0x0:0x0:0x0:0x0:0x0
0x10208ae4:0x0:0x0:0x0:0x0:0x0
0x10208ae8:0x0:0x0:0x0:0x0:0x0
0x10208aec:0x0:0x0:0x0:0x0:0x0
0x10208af0:0x0:0x0:0x0:0x0:0x0
0x10208af4:0x0:0x0:0x0:0x0:0x0
0x10208af8:0xc0000020:0x5:0x101e80:0x0
0x10208afc:0xc0000120:0x100:0x1cc10040
**Dump systracker debug register end**
Signed-off-by: Zexin Wang <ot_zexin.wang@mediatek.corp-partner.google.com>
Change-Id: Icb34c87adc099172abdfc9868ff8e30287e61be0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Extract the common parts of the mt8196 tracker driver into tracker_v3 to
improve code reusability.
BUG=b:379008996
BRANCH=skywalker
TEST=build passed.
Signed-off-by: Zexin Wang <ot_zexin.wang@mediatek.corp-partner.google.com>
Change-Id: If71bffe03cd2c30a0e9b3057c39667c1c2fdcb62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Create the ojal variant of the ocelot reference board by copying the
ocelot files to a new directory named for the variant.
BUG=b:437459757
TEST=1. Build emerge-ocelot
2. Run part_id_gen tool without any errors
Change-Id: Ic2fc86d89facae21b9bed898ebe518d316d953da
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
`src/mainboard/*/common` doesn't need a Kconfig.name, so don't check
for one.
Change-Id: I6c69c174287f7f068e28ed9c33b9b5542c87ca60
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89051
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Adjust the linter to skip `common` directories, as a board_info.txt
serves no purpose there.
This also changes `sort | uniq` to `sort -u` for efficiency.
Change-Id: I29639d8b620bcd4f2f7032802f375d79ac391535
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89050
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Trying to read a firmware binary for Turin platform results in
"Invalid address(41400) or mode(0)" error. The utility does not
respect the address mode set by the directory header. The address
mode of th entries is valid only if the address mode of the directory
is equal to 2 or 3.
Check the address mode of the directory and use it for entries only
when its value is less than 2.
TEST=Successfuly parse vendor BIOS for Gigabyte MZ33-AR1.
Change-Id: I479bc846bfb334231fdc707274a8ac44b6c384d4
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
According to AMD documentation, starting from Family 17h Models
00h-0Fh, the PSP on-chip boot loader reads the PSP directory pointer
from offset 0x14 in the Embedded Firmware structure, replacing the
previous offset 0x10.
The docs do not specify any special value indicating a change of
offset. Some AMI binaries use a zero address in this directory field,
which caused incorrect offset handling.
Change-Id: I67ab763d070a9580a8269b525b203c932c5b1b95
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Intel ifdtool can dump the Intel Firmware Descriptor, which is helpful
for debugging and inspecting firmware binaries. This utility lacked
similar functionality, so this patch introduces a `--dump` CLI option
to display decoded information from the embedded firmware header.
Currently, the output includes SPI frequency and read mode for various
AMD family models.
Change-Id: Ideb1076f1d580496dac293882007cfa4672d188b
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Added support for new mainboard configurations, `ptlrvp_chromeec4es`
and `ptlrvp4es`, to the Intel PTLRVP platform. These configurations
extend the existing options for pre-production silicon of the
Panther Lake SoC.
BUG=none
TEST=Build with new configurations to ensure successful compilation and
correct feature selections.
Change-Id: I3f716ab71a97d02b1694858d966f8111f18adff3
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88997
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates the DRAM memory reservation range for TF-A
to align with the latest Bluey memory layout specifications.
TEST=Verified boot up on google/bluey.
Change-Id: Ifb67e591d0f3d28cd6b0856198b29af49c2aab4c
Signed-off-by: smadhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
