mb/google/ocelot: Create matsu variant
Create the matsu variant of the ocelot reference board by copying
the ocelot files to a new directory named for the variant.
BUG=b:443612246
TEST=1. util/abuild/abuild -p none -t google/ocelot -x -a
make sure the build includes GOOGLE_MATSU
2. Run part_id_gen tool without any errors
Change-Id: I81d010fdda927db56d7b41ddc527c1c40b2cf768
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit is contained in:
Ivy Jian
Matt DeVillier
parent
76e0f64035
commit
6074ca18d3
13 changed files with 660 additions and 0 deletions
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@ -56,6 +56,12 @@ config BOARD_GOOGLE_BASEBOARD_OCELOT
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select SYSTEM_TYPE_LAPTOP
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select TPM_GOOGLE_TI50
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config BOARD_GOOGLE_MODEL_MATSU
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def_bool n
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select BOARD_GOOGLE_BASEBOARD_OCELOT
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select FSP_UGOP_EARLY_SIGN_OF_LIFE
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select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
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config BOARD_GOOGLE_MODEL_OCELOT
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def_bool n
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select BOARD_GOOGLE_BASEBOARD_OCELOT
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@ -74,6 +80,9 @@ config BOARD_GOOGLE_MODEL_OJAL
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select EC_GOOGLE_CHROMEEC_RTK
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select EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE
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config BOARD_GOOGLE_MATSU
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select BOARD_GOOGLE_MODEL_MATSU
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config BOARD_GOOGLE_OCELOT
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select BOARD_GOOGLE_MODEL_OCELOT
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@ -130,6 +139,7 @@ config DRIVER_TPM_I2C_ADDR
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config DRIVER_TPM_I2C_BUS
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hex
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default 0x01 if BOARD_GOOGLE_MODEL_MATSU
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default 0x01 if BOARD_GOOGLE_MODEL_OCELOT
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default 0x01 if BOARD_GOOGLE_MODEL_OJAL
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@ -144,6 +154,7 @@ config MAINBOARD_FAMILY
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default "Google_Ocelot"
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config MAINBOARD_PART_NUMBER
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default "Matsu" if BOARD_GOOGLE_MODEL_MATSU
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default "Ocelot" if BOARD_GOOGLE_MODEL_OCELOT
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default "Ojal" if BOARD_GOOGLE_OJAL
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@ -154,6 +165,7 @@ config MEMORY_SOLDERDOWN
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config TPM_TIS_ACPI_INTERRUPT
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int
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default 78 if BOARD_GOOGLE_MODEL_MATSU # GPE0_DW2_14 (GPP_E14)
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default 49 if BOARD_GOOGLE_MODEL_OCELOT # GPE0_DW1_17 (GPP_B17)
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default 49 if BOARD_GOOGLE_MODEL_OJAL # GPE0_DW1_17 (GPP_B17)
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@ -166,6 +178,7 @@ config USE_PM_ACPI_TIMER
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config VARIANT_DIR
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string
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default "matsu" if BOARD_GOOGLE_MODEL_MATSU
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default "ocelot" if BOARD_GOOGLE_MODEL_OCELOT
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default "ojal" if BOARD_GOOGLE_MODEL_OJAL
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@ -2,6 +2,9 @@
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comment "Ocelot"
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config BOARD_GOOGLE_MATSU
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bool "-> Matsu"
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config BOARD_GOOGLE_OCELOT
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bool "-> Ocelot"
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@ -15,6 +15,8 @@
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//TODO for Nuvo: #define EC_SYNC_IRQ GPP_E07_IRQ
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#if CONFIG(BOARD_GOOGLE_MODEL_OCELOT) || CONFIG(BOARD_GOOGLE_MODEL_OJAL)
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#define EC_SYNC_IRQ 0 /* Not Connected */
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#elif CONFIG(BOARD_GOOGLE_MODEL_MATSU)
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#define EC_SYNC_IRQ GPP_E08_IRQ
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#endif
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#define GPIO_PCH_WP GPP_D02
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#define GPIO_SLP_S0_GATE GPP_C08
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6
src/mainboard/google/ocelot/variants/matsu/Makefile.mk
Normal file
6
src/mainboard/google/ocelot/variants/matsu/Makefile.mk
Normal file
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@ -0,0 +1,6 @@
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## SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += gpio.c
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romstage-y += gpio.c
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romstage-y += memory.c
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ramstage-y += gpio.c
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391
src/mainboard/google/ocelot/variants/matsu/gpio.c
Normal file
391
src/mainboard/google/ocelot/variants/matsu/gpio.c
Normal file
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@ -0,0 +1,391 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <boardid.h>
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#include <soc/gpio.h>
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/* Pad configuration in ramstage*/
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static const struct pad_config gpio_table[] = {
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/* GPP_A */
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/* GPP_A00: ESPI_IO0_AIC */
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/* GPP_A00 : GPP_A00 ==> ESPI_IO0_EC_R configured on reset, do not touch */
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/* GPP_A01: ESPI_IO1_AIC */
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/* GPP_A01 : GPP_A01 ==> ESPI_IO1_EC_R configured on reset, do not touch */
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/* GPP_A02: ESPI_IO2_AIC */
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/* GPP_A02 : GPP_A02 ==> ESPI_IO2_EC_R configured on reset, do not touch */
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/* GPP_A03: ESPI_IO3_AIC */
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/* GPP_A03 : GPP_A03 ==> ESPI_IO3_EC_R configured on reset, do not touch */
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/* GPP_A04: ESPI_CS0_AIC_N */
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/* GPP_A04 : GPP_A04 ==> ESPI_CS0_HDR_L configured on reset, do not touch */
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/* GPP_A05: ESPI_CLK_AIC */
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/* GPP_A05 : GPP_A05 ==> ESPI_CLK_HDR configured on reset, do not touch */
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/* GPP_A06: ESPI_RST_AIC_N */
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/* GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */
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/* GPP_A08: M2_GEN4_SSD_RESET_N */
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PAD_CFG_GPO(GPP_A08, 1, PLTRST),
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/* GPP_A09: M.2_WWAN_FCP_OFF_N */
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PAD_CFG_GPO(GPP_A09, 1, PLTRST),
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/* GPP_A10: WWAN_DISABLE_N */
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PAD_CFG_GPO(GPP_A10, 1, PLTRST),
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/* GPP_A11: WLAN_RST_N */
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PAD_CFG_GPO(GPP_A11, 1, PLTRST),
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/* GPP_A12: WIFI_WAKE_N */
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PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL),
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/* GPP_A13: PCIE_LNK_DOWN */
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PAD_CFG_NF_OWNERSHIP(GPP_A13, NONE, DEEP, NF2, ACPI),
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/* GPP_A15: CODEC_GPIO_EN */
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PAD_CFG_GPO(GPP_A15, 1, DEEP),
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/* GPP_B */
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/* GPP_B00: USBC_SML_CLK_PD */
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PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1),
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/* GPP_B01: USBC_SML_DATA_PD */
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PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1),
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/* GPP_B02: ISH_I2C0_SDA_SNSR_HDR */
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PAD_NC(GPP_B02, NONE),
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/* GPP_B03: ISH_I2C0_SCL_SNSR_HDR */
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PAD_NC(GPP_B03, NONE),
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/* GPP_B04: ISH_GP_0_SNSR_HDR */
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PAD_NC(GPP_B04, NONE),
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/* GPP_B06: SOC_PDB_CTRL */
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PAD_CFG_GPO(GPP_B06, 0, DEEP),
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/* GPP_B08: ISH_GP_4_SNSR_HDR */
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PAD_NC(GPP_B08, NONE),
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/* GPP_B09: BT_RF_KILL_N */
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PAD_CFG_GPO(GPP_B09, 1, DEEP),
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/* GPP_B10: NC */
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PAD_NC(GPP_B10, NONE),
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/* GPP_B12: PM_SLP_S0_N */
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PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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/* GPP_B13: PLT_RST_N */
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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/* GPP_B14: GPP_B14_DDSP_HPDB */
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PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
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/* GPP_B16: COINLESS_MODE_SELECT */
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PAD_CFG_GPI(GPP_B16, NONE, DEEP),
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/* GPP_B17: SPI_TPM_INT_N */
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PAD_CFG_GPI_APIC_LOCK(GPP_B17, NONE, LEVEL, INVERT, LOCK_CONFIG),
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/* GPP_B20: WWAN_RST_N */
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PAD_CFG_GPO(GPP_B20, 1, PLTRST),
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/* GPP_B21: TCP_RETIMER_FORCE_PWR */
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PAD_CFG_GPO(GPP_B21, 0, DEEP),
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/* GPP_B24: ESPI_ALERT0_EC_R_N */
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PAD_NC(GPP_B24, NONE),
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/* GPP_B25: None */
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PAD_NC(GPP_B25, NONE),
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/* GPP_C */
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/* GPP_C00: SPD_SMB_CLK */
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PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
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/* GPP_C01: SPD_SMB_DATA */
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PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
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/* GPP_C02: NC */
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PAD_NC(GPP_C02, NONE),
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/* GPP_C03: TCP_LAN_SML0_SCL_R */
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PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
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/* GPP_C04: TCP_LAN_SML0_SDA_R */
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PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
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/* GPP_C05: NC */
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PAD_NC(GPP_C05, NONE),
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/* GPP_C06: NC */
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PAD_NC(GPP_C06, NONE),
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/* GPP_C07: NC */
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PAD_NC(GPP_C07, NONE),
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/* GPP_C08: PM_SLP_S0_N_GPP_CNTRL */
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PAD_CFG_GPO(GPP_C08, 1, PLTRST),
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/* GPP_C09: CLKREQ0_X1_GEN4_M2_WLAN_N */
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PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1),
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/* GPP_C10: WIFI_RF_KILL_N */
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PAD_CFG_GPO(GPP_C10, 1, DEEP),
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/* GPP_C11: CLKREQ2_X4_GEN4_DT_CEM_SLOT1_N */
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PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
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/* GPP_C12: CLKREQ3_X4_GEN4_M2_SSD_N */
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PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
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/* GPP_C13: CLKREQ4_X4_GEN4_DT_CEM_SLOT2_N */
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PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
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/* GPP_C14: CLKREQ5_X1_GEN1_GBE_LAN_N */
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PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
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/* GPP_C15: FPS_RST_N */
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PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG),
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/* GPP_C16: MOD_TCSS1_LS_TX_DDC_SCL */
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PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
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/* GPP_C17: MOD_TCSS1_LS_RX_DDC_SDA */
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PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
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/* GPP_C18: MOD_TCSS2_LS_TX_DDC_SCL */
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PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
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/* GPP_C19: MOD_TCSS2_LS_RX_DDC_SDA */
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PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
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/* GPP_C22: DDPB_HDMI_CTRLCLK */
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PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),
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/* GPP_C23: DDPB_HDMI_CTRLDATA */
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PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
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/* GPP_D */
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/* GPP_D01: MOD_TCSS1_TYP_A_VBUS_EN */
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PAD_CFG_GPO(GPP_D01, 1, DEEP),
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/* GPP_D02: SOC_WP_OD */
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PAD_CFG_GPO(GPP_D02, 0, DEEP),
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/* GPP_D03: X4_SLOT_WAKE_N */
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PAD_CFG_GPI_SCI_LOW(GPP_D03, NONE, DEEP, LEVEL),
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/* GPP_D07: ISH_UART0_RTS_N_SNSR_HDR */
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PAD_NC(GPP_D07, NONE),
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/* GPP_D08: ISH_UART0_CTS_N_SNSR_HDR */
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PAD_NC(GPP_D08, NONE),
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/* GPP_D09: I2S_MCLK_HDR */
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PAD_CFG_NF(GPP_D09, NONE, DEEP, NF1),
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/* GPP_D10: HDA_BCLK (HDR) */
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PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
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/* GPP_D11: HDA_SYNC (HDR) */
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PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
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/* GPP_D12: HDA_SDO (HDR) */
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PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
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/* GPP_D13: HDA_SDI0 (HDR) */
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PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
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/* GPP_D16: HDA_RST_N (HDR) */
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PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
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/* GPP_D17: HDA_SDI1 (HDR) */
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PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
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/* GPP_D19: NC */
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PAD_NC(GPP_D19, NONE),
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/* GPP_D21: GPP_D21_UFS_REFCLK_R */
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PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
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/* GPP_E */
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/* GPP_E01: PM_SLP_DRAM_N */
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PAD_CFG_NF(GPP_E01, NONE, DEEP, NF2),
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/* GPP_E02: NC */
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PAD_NC(GPP_E02, NONE),
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/* GPP_E03: X4_DT_PCIE_RST_N */
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PAD_CFG_GPO(GPP_E03, 1, PLTRST),
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/* GPP_E05: GPP_E5_FPS_PWREN */
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PAD_CFG_GPO(GPP_E05, 1, DEEP),
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/* GPP_E06: GPP_E6_PEN_DETECT */
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PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, DEEP, LEVEL, ACPI),
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/* GPP_E07: LAN_GPIO_RST_N */
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PAD_CFG_GPO(GPP_E07, 1, PLTRST),
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/* GPP_E08: EC_SOC_INT_ODL */
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PAD_CFG_GPI(GPP_E08, NONE, DEEP),
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/* GPP_E09: USB_FP_CONN_1_CONN_2_OC0_N */
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PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),
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/* GPP_E10: M2_UFS_DET_SEL_N */
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PAD_CFG_GPI(GPP_E10, NONE, DEEP),
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/* GPP_E11: THC0_SPI1_CLK_TCH_PNL1 */
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PAD_CFG_NF(GPP_E11, NONE, DEEP, NF3),
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/* GPP_E12: THC_I2C0_SCL_TCH_PNL1 */
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PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3),
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/* GPP_E13: THC_I2C0_SDA_TCH_PNL1 */
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PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3),
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/* GPP_E14: THC0_SPI1_IO_2_TCH_PNL1 */
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PAD_CFG_NF(GPP_E14, NONE, DEEP, NF3),
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/* GPP_E15: THC0_SPI1_IO_3_TCH_PNL1 */
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PAD_CFG_NF(GPP_E15, NONE, DEEP, NF3),
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/* GPP_E16: THC0_SPI1_RST_N_TCH_PNL1 */
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PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1),
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/* GPP_E17: GPP_E17_GSPI0A_CS0 */
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PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5),
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/* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */
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PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
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/* GPP_E19: FPS_INT_N */
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PAD_CFG_GPI_IRQ_WAKE(GPP_E19, NONE, PWROK, LEVEL, INVERT),
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/* GPP_E20: FPS_FW_UPDATE */
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PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG),
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/* GPP_E21: I2C_PMC_PD_INT_N */
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PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
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/* GPP_E22: NC */
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PAD_NC(GPP_E22, NONE),
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/* GPP_F */
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/* GPP_F00: M.2_CNV_BRI_DT_BT_UART2_RTS_N */
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PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1),
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/* GPP_F01: M.2_CNV_BRI_RSP_BT_UART2_RXD */
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PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1),
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/* GPP_F02: M.2_CNV_RGI_DT_BT_UART2_TXD */
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PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1),
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/* GPP_F03: M.2_CNV_RGI_RSP_BT_UART2_CTS_N */
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PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1),
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/* GPP_F04: CNV_RF_RESET_R_N */
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PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
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/* GPP_F05: CRF_CLKREQ_R */
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PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
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/* GPP_F06: DISC_WLAN_WWAN_COEX3 */
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PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1),
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/* GPP_F07: FUSA_DIAGTEST_EN_HDR */
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PAD_CFG_NF(GPP_F07, NONE, DEEP, NF2),
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/* GPP_F08: TCH_PNL1_PWR_EN */
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PAD_CFG_GPO(GPP_F08, 1, PLTRST),
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/* GPP_F09: M2_UFS_RST_N */
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PAD_CFG_GPO(GPP_F09, 1, DEEP),
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/* GPP_F10: X4_PCIE_SLOT1_PWR_EN */
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PAD_CFG_GPO(GPP_F10, 1, PLTRST),
|
||||
/* GPP_F11: THC1_SPI2_CLK_TCH_PNL2 */
|
||||
PAD_CFG_NF(GPP_F11, NONE, DEEP, NF11),
|
||||
/* GPP_F12: THC_I2C1_SCL_TCH_PAD */
|
||||
PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
|
||||
/* GPP_F13: THC_I2C1_SDA_TCH_PAD */
|
||||
PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
|
||||
/* GPP_F14: GPP_F14_GPSI0A_MOSI */
|
||||
PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8),
|
||||
/* GPP_F15: GPP_F15_GSPI0A_MISO */
|
||||
PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
|
||||
/* GPP_F16: GPP_F16_GSPI0A_CLK */
|
||||
PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8),
|
||||
/* GPP_F17: CODEC_IRQ_HDR */
|
||||
PAD_CFG_GPI(GPP_F17, NONE, DEEP),
|
||||
/* GPP_F18: TCH_PAD_INT_N */
|
||||
PAD_CFG_GPI_APIC_DRIVER(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT),
|
||||
/* GPP_F19: NC */
|
||||
PAD_NC(GPP_F19, NONE),
|
||||
/* GPP_F20: CSE_EARLY_SW */
|
||||
PAD_CFG_GPI(GPP_F20, NONE, DEEP),
|
||||
/* GPP_F22: THC1_SPI2_DSYNC */
|
||||
PAD_CFG_NF(GPP_F22, NONE, DEEP, NF3),
|
||||
|
||||
/* GPP_H */
|
||||
/* GPP_H00: NC */
|
||||
PAD_NC(GPP_H00, NONE),
|
||||
/* GPP_H01: M2_UFS_SLP_N */
|
||||
PAD_CFG_GPO(GPP_H01, 1, DEEP),
|
||||
/* GPP_H02: DEBUG_TRACE_PNP */
|
||||
PAD_CFG_GPO(GPP_H02, 1, PLTRST),
|
||||
/* GPP_H03: MIC MUTE */
|
||||
PAD_CFG_NF(GPP_H03, NONE, DEEP, NF1),
|
||||
/* GPP_H04: CNV_MFUART2_RXD */
|
||||
PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1),
|
||||
/* GPP_H05: CNV_MFUART2_TXD */
|
||||
PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1),
|
||||
/* GPP_H06: I2C3_SCL_AUDIO_HDR */
|
||||
PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
|
||||
/* GPP_H07: I2C3_SDA_AUDIO_HDR */
|
||||
PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
|
||||
/* GPP_H08: SOC_BIOS_LOG_TTK_UART_RX */
|
||||
PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
|
||||
/* GPP_H09: SOC_BIOS_LOG_TTK_UART_TX */
|
||||
PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
|
||||
/* GPP_H10: UART0_BUF_RTS */
|
||||
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
|
||||
/* GPP_H11: UART0_BUF_CTS */
|
||||
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),
|
||||
/* GPP_H13: CPU_C10_GATE_N_R */
|
||||
PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
|
||||
/* GPP_H14: ISH_I3C1_SDA_SNSR_HDR */
|
||||
PAD_NC(GPP_H14, NONE),
|
||||
/* GPP_H15: ISH_I3C1_SCL_SNSR_HDR */
|
||||
PAD_NC(GPP_H15, NONE),
|
||||
/* GPP_H17: MIC MUTE LED */
|
||||
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
|
||||
/* GPP_H18: GEN4_SSD_PWREN */
|
||||
PAD_CFG_GPO(GPP_H18, 1, DEEP),
|
||||
/* GPP_H19: I3C0_SDA_HDR */
|
||||
PAD_CFG_NF(GPP_H19, NONE, DEEP, NF2),
|
||||
/* GPP_H20: I3C0_SCL_HDR */
|
||||
PAD_CFG_NF(GPP_H20, NONE, DEEP, NF2),
|
||||
/* GPP_H21: I2C1_SDA_TTK_CHROME */
|
||||
PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
|
||||
/* GPP_H22: I2C1_SCL_TTK_CHROME */
|
||||
PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
|
||||
/* GPP_H23: TP */
|
||||
PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1),
|
||||
/* GPP_H24: TP */
|
||||
PAD_CFG_NF(GPP_H24, NONE, DEEP, NF1),
|
||||
|
||||
/* GPP_V */
|
||||
/* GPP_V00: PM_BATLOW_N */
|
||||
PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
|
||||
/* GPP_V01: BC_ACOK_MCP */
|
||||
PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
|
||||
/* GPP_V02: LANWAKE_N_R */
|
||||
PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
|
||||
/* GPP_V03: PWRBTN_MCP_N */
|
||||
PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
|
||||
/* GPP_V04: PM_SLP_S3_N */
|
||||
PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
|
||||
/* GPP_V05: PM_SLP_S4_N */
|
||||
PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
|
||||
/* GPP_V06: PM_SLP_A_N */
|
||||
PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),
|
||||
/* GPP_V07: M.2_BTWIFI_SUS_CLK_LS */
|
||||
PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1),
|
||||
/* GPP_V08: SLP_WLAN_N */
|
||||
PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
|
||||
/* GPP_V09: PM_SLP_S5_N */
|
||||
PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
|
||||
/* GPP_V10: LANPHYPC_R_N */
|
||||
PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1),
|
||||
/* GPP_V11: PM_SLP_LAN_N */
|
||||
PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),
|
||||
/* GPP_V12: WAKE_N */
|
||||
PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
|
||||
/* GPP_V13: GPP_V13_CATERR_N */
|
||||
PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1),
|
||||
/* GPP_V14: GPP_V14_FORCEPR_N */
|
||||
PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1),
|
||||
/* GPP_V15: GPP_V15_THERMTRIP_N */
|
||||
PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1),
|
||||
/* GPP_V16: GPP_V16_VCCST_EN */
|
||||
PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1),
|
||||
};
|
||||
|
||||
/* Early pad configuration in bootblock */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
/* GPP_B17: SPI_TPM_INT_N */
|
||||
PAD_CFG_GPI_APIC(GPP_B17, NONE, DEEP, LEVEL, INVERT),
|
||||
/* GPP_H06: I2C3_SDA_PSS */
|
||||
PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
|
||||
/* GPP_H07: I2C3_SCL_PSS */
|
||||
PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
|
||||
/* GPP_H08: SOC_BIOS_LOG_TTK_UART_RX */
|
||||
PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
|
||||
/* GPP_H09: SOC_BIOS_LOG_TTK_UART_TX */
|
||||
PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
|
||||
/* GPP_H21: I2C1_SDA_TTK_CHROME */
|
||||
PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
|
||||
/* GPP_H22: I2C1_SCL_TTK_CHROME */
|
||||
PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
|
||||
};
|
||||
|
||||
/* Pad configuration in romstage */
|
||||
static const struct pad_config romstage_gpio_table[] = {
|
||||
/* GPP_C00: SPD_SMB_CLK */
|
||||
PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
|
||||
/* GPP_C01: SPD_SMB_DATA */
|
||||
PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
|
||||
/* GPP_C15: FPS_RST_N */
|
||||
PAD_CFG_GPO(GPP_C15, 0, PLTRST),
|
||||
};
|
||||
|
||||
const struct pad_config *variant_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(gpio_table);
|
||||
return gpio_table;
|
||||
}
|
||||
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(early_gpio_table);
|
||||
return early_gpio_table;
|
||||
}
|
||||
|
||||
/* Create the stub for romstage gpio, typically use for power sequence */
|
||||
const struct pad_config *variant_romstage_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(romstage_gpio_table);
|
||||
return romstage_gpio_table;
|
||||
}
|
||||
|
||||
static const struct cros_gpio cros_gpios[] = {
|
||||
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE0_NAME),
|
||||
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME),
|
||||
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE2_NAME),
|
||||
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE3_NAME),
|
||||
CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE4_NAME),
|
||||
};
|
||||
|
||||
DECLARE_CROS_GPIOS(cros_gpios);
|
||||
126
src/mainboard/google/ocelot/variants/matsu/hda_verb.c
Normal file
126
src/mainboard/google/ocelot/variants/matsu/hda_verb.c
Normal file
|
|
@ -0,0 +1,126 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* coreboot specific header */
|
||||
0x10ec0256, /* Codec Vendor / Device ID: Realtek ALC256 */
|
||||
0x10ec12ac, /* Subsystem ID */
|
||||
0x00000013, /* Number of jacks (NID entries) */
|
||||
|
||||
AZALIA_RESET(0x1),
|
||||
/* NID 0x01, HDA Codec Subsystem ID Verb Table */
|
||||
AZALIA_SUBVENDOR(0, 0x10ec12ac),
|
||||
|
||||
/* Pin Widget Verb Table */
|
||||
/*
|
||||
* DMIC
|
||||
* Requirement is to use PCH DMIC. Hence,
|
||||
* commented out codec's Internal DMIC.
|
||||
* AZALIA_PIN_CFG(0, 0x12, 0x90A60130),
|
||||
* AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
*/
|
||||
/* Pin widget 0x14 - Front (Port-D) */
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
/* Pin widget 0x18 - NPC */
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111F0),
|
||||
/* Pin widget 0x19 - MIC2 (Port-F) */
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x04A11040),
|
||||
/* Pin widget 0x1A - LINE1 (Port-C) */
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111F0),
|
||||
/* Pin widget 0x1B - NPC */
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111F0),
|
||||
/* Pin widget 0x1D - BEEP-IN */
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40610041),
|
||||
/* Pin widget 0x1E - NPC */
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111F0),
|
||||
/* Pin widget 0x21 - HP1-OUT (Port-I) */
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x04211020),
|
||||
/*
|
||||
* Widget node 0x20 - 1
|
||||
* Codec hidden reset and speaker power 2W/4ohm
|
||||
*/
|
||||
0x0205001A,
|
||||
0x0204C003,
|
||||
0x02050038,
|
||||
0x02047901,
|
||||
/*
|
||||
* Widget node 0x20 - 2
|
||||
* Class D power on Reset
|
||||
*/
|
||||
0x0205003C,
|
||||
0x02040354,
|
||||
0x0205003C,
|
||||
0x02040314,
|
||||
/*
|
||||
* Widget node 0x20 - 3
|
||||
* Disable AGC and set AGC limit to -1.5dB
|
||||
*/
|
||||
0x02050016,
|
||||
0x02040C50,
|
||||
0x02050012,
|
||||
0x0204EBC1,
|
||||
/*
|
||||
* Widget node 0x20 - 4
|
||||
* Set AGC Post gain +1.5dB then Enable AGC
|
||||
*/
|
||||
0x02050013,
|
||||
0x02044023,
|
||||
0x02050016,
|
||||
0x02040E50,
|
||||
/*
|
||||
* Widget node 0x20 - 5
|
||||
* Silence detector enabling + Set EAPD to verb control
|
||||
*/
|
||||
0x02050037,
|
||||
0x0204FE15,
|
||||
0x02050010,
|
||||
0x02040020,
|
||||
/*
|
||||
* Widget node 0x20 - 6
|
||||
* Silence data mode Threshold (-90dB)
|
||||
*/
|
||||
0x02050030,
|
||||
0x0204A000,
|
||||
0x0205001B,
|
||||
0x02040A4B,
|
||||
/*
|
||||
* Widget node 0x20 - 7
|
||||
* Default setting-1
|
||||
*/
|
||||
0x05750003,
|
||||
0x05740DA3,
|
||||
0x02050046,
|
||||
0x02040004,
|
||||
/*
|
||||
* Widget node 0x20 - 8
|
||||
* support 1 pin detect two port
|
||||
*/
|
||||
0x02050009,
|
||||
0x0204E003,
|
||||
0x0205000A,
|
||||
0x02047770,
|
||||
/*
|
||||
* Widget node 0x20 - 9
|
||||
* To set LDO1/LDO2 as default
|
||||
*/
|
||||
0x02050008,
|
||||
0x02046A0C,
|
||||
0x02050008,
|
||||
0x02046A0C,
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {
|
||||
/* Dos beep path - 1 */
|
||||
0x01470C00,
|
||||
0x02050036,
|
||||
0x02047151,
|
||||
0x01470740,
|
||||
/* Dos beep path - 2 */
|
||||
0x0143b000,
|
||||
0x01470C02,
|
||||
0x01470C02,
|
||||
0x01470C02,
|
||||
};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef MAINBOARD_EC_H
|
||||
#define MAINBOARD_EC_H
|
||||
|
||||
#include <baseboard/ec.h>
|
||||
|
||||
#endif /* MAINBOARD_GPIO_H */
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef __MAINBOARD_GPIO_H__
|
||||
#define __MAINBOARD_GPIO_H__
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
|
||||
/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
|
||||
#define GPE_EC_WAKE GPE0_LAN_WAK
|
||||
|
||||
#endif /* __MAINBOARD_GPIO_H__ */
|
||||
69
src/mainboard/google/ocelot/variants/matsu/memory.c
Normal file
69
src/mainboard/google/ocelot/variants/matsu/memory.c
Normal file
|
|
@ -0,0 +1,69 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <soc/romstage.h>
|
||||
|
||||
static const struct mb_cfg lp5_mem_config = {
|
||||
.type = MEM_TYPE_LP5X,
|
||||
|
||||
.lpx_dq_map = {
|
||||
.ddr0 = {
|
||||
.dq0 = { 10, 11, 8, 9, 15, 14, 12, 13, },
|
||||
.dq1 = { 7, 4, 5, 6, 3, 0, 2, 1 },
|
||||
},
|
||||
.ddr1 = {
|
||||
.dq0 = { 8, 11, 10, 9, 15, 12, 13, 14, },
|
||||
.dq1 = { 6, 7, 5, 4, 1, 3, 0, 2 },
|
||||
},
|
||||
.ddr2 = {
|
||||
.dq0 = { 3, 2, 1, 0, 6, 7, 5, 4, },
|
||||
.dq1 = { 9, 8, 10, 11, 15, 12, 13, 14 },
|
||||
},
|
||||
.ddr3 = {
|
||||
.dq0 = { 8, 11, 10, 9, 15, 13, 12, 14, },
|
||||
.dq1 = { 4, 5, 6, 7, 1, 3, 2, 0 },
|
||||
},
|
||||
},
|
||||
|
||||
.lpx_dqs_map = {
|
||||
.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
|
||||
.ddr1 = { .dqs0 = 1, .dqs1 = 0 },
|
||||
.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
.ddr3 = { .dqs0 = 1, .dqs1 = 0 },
|
||||
},
|
||||
|
||||
.ect = true, /* Early Command Training */
|
||||
|
||||
.lp_ddr_dq_dqs_re_training = 1,
|
||||
|
||||
.user_bd = BOARD_TYPE_ULT_ULX,
|
||||
|
||||
.lp5x_config = {
|
||||
.ccc_config = 0xFF,
|
||||
},
|
||||
};
|
||||
|
||||
const struct mb_cfg *variant_memory_params(void)
|
||||
{
|
||||
return &lp5_mem_config;
|
||||
}
|
||||
|
||||
int variant_memory_sku(void)
|
||||
{
|
||||
/*
|
||||
* Memory configuration board straps
|
||||
* GPIO_MEM_CONFIG_0 GPP_H23
|
||||
* GPIO_MEM_CONFIG_1 GPP_H24
|
||||
* GPIO_MEM_CONFIG_2 GPP_B06
|
||||
* GPIO_MEM_CONFIG_3 GPP_B08
|
||||
*/
|
||||
gpio_t spd_gpios[] = {
|
||||
GPP_H23,
|
||||
GPP_H24,
|
||||
GPP_B06,
|
||||
GPP_B08,
|
||||
};
|
||||
|
||||
return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
|
||||
}
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
# This is an auto-generated file. Do not edit!!
|
||||
# Generated by:
|
||||
# ./util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/ocelot/variants/matsu/memory src/mainboard/google/ocelot/variants/matsu/memory/mem_parts_used.txt
|
||||
|
||||
SPD_SOURCES =
|
||||
SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 0(0b0000) Parts = H58G56BK8BX068
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
# This is an auto-generated file. Do not edit!!
|
||||
# Generated by:
|
||||
# ./util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/ocelot/variants/matsu/memory src/mainboard/google/ocelot/variants/matsu/memory/mem_parts_used.txt
|
||||
|
||||
DRAM Part Name ID to assign
|
||||
H58G56BK8BX068 0 (0000)
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
# This is a CSV file containing a list of memory parts used by this variant.
|
||||
# One part per line with an optional fixed ID in column 2.
|
||||
# Only include a fixed ID if it is required for legacy reasons!
|
||||
# Generated IDs are dependent on the order of parts in this file,
|
||||
# so new parts must always be added at the end of the file!
|
||||
#
|
||||
# Generate an updated Makefile.mk and dram_id.generated.txt by running the
|
||||
# part_id_gen tool from util/spd_tools.
|
||||
# See util/spd_tools/README.md for more details and instructions.
|
||||
|
||||
# Part Name
|
||||
H58G56BK8BX068
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
chip soc/intel/pantherlake
|
||||
|
||||
device domain 0 on
|
||||
end
|
||||
end
|
||||
Loading…
Add table
Add a link
Reference in a new issue