Provide a weak devtree_update() hook and invoke it early in ramstage
at BS_PRE_DEVICE. Mainboards can override devtree_update() to
enable/disable devices at runtime based on CMOS/NVRAM settings.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic84ddb25e1da050543c230ea457042b8a8a3061f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Some silicon initialization modules, like OpenSIL report bus width
extension as 16 bits for ECC for DDR5 memories. Handle this case
correctly for DDR5 and LPDDR5 memories by reporting appropriate
bitfield of the SPD width. This field is used later by coreboot to
calculate the bus extension again, which results in 16bit extension
for ECC.
Change-Id: Ia0a9c221a5d047dd7feb212027f5da2399ccb8e1
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Without explicit DDR5 support, print_spd_info() was decoding DDR5 DIMMs
with the DDR4 SPD layout, so banks, ranks, rows, columns, and module
size were all displaying incorrect values.
Add DDR5-specific decoding in spd_bin.c using JESD400-5 byte positions.
Define these offsets in ddr5.h and branch in each getter when
dram_type is DDR5 so printed SPD info matches the actual module.
Fix printk reporting DIMM module size to only report "per channel" when
the DIMM actually contains multiple channels.
TEST=build/boot on out-of-tree board Erying SRMJ4 and Starlabs Starbook
MTL. Verify DIMM info printed in cbmem console is correct.
Change-Id: I7f418db3f89c67c2a71b2c327bb511a78faf7300
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91145
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for dynamic text scaling based on the display resolution
to ensure bootsplash text remains legible on high-density panels.
Key changes:
- Implement get_resolution_scale() to determine a scaling factor (1x,
2x, or 3x) based on the panel's major dimension (HD, QHD, or 4K).
- Update draw_char() to render glyphs as scaled blocks, repeating each
font pixel across a square of the calculated scale factor.
- Apply the scaling factor to all text layout calculations, including
kerning, character advance, and total string dimensions.
- Ensure anti-aliasing (alpha blending) is correctly applied to each
individual pixel within the scaled blocks.
Change-Id: I8b22019ddaa46f1a24f38d565d946bb28a213791
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Transition the bootsplash text renderer from 1-bit monochrome bitmaps
to 8-bit alpha maps to support text smoothing (anti-aliasing).
Key changes:
- Update fonts.h to declare font_table as a 2D uint8_t array containing
alpha intensity values (0-255) for each pixel.
- Update draw_char() to perform alpha blending by mixing the text color
with the existing background pixel using the formula:
Result = (Color * Alpha + BG * (255 - Alpha)) / 255.
- Regenerate the font table data to reflect the new 8-bit format and
updated character widths.
Change-Id: I9d4dde74d86fd552b30523f3b8ff34fb8fdba782
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Enable rendering of system status messages during the `low-battery`
bootsplash sequence when `FRAMEBUFFER_SPLASH_TEXT` Kconfig is enabled.
This change adds a 32-byte buffer to capture platform-specific text
(such as battery status) and draws it at the footer of the framebuffer
alongside the logo.
TEST=Able to build and boot google/fatcat.
Change-Id: I298804869eb909201a9056b83e4954e223e2b9bb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Introduce FRAMEBUFFER_SPLASH_TEXT to allow rendering status messages
directly into the linear framebuffer. This enables displaying dynamic
information, such as battery levels or system status, during the
bootsplash stage without requiring complex graphics libraries.
Changes:
- Add Kconfig option to toggle framebuffer text support.
- User to call `render_text_to_framebuffer` to display the text message.
- Include render_text.c in ramstage build when
FRAMEBUFFER_SPLASH_TEXT is enabled.
- Create 24x32 font table entry using GoogleSansFlex_24pt-Medium.ttf.
TEST=Able to build google/fatcat.
Change-Id: I6ac25d8d8a9d3d77a9cc2f8c6e0139268b2066b9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91092
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Expose calculate_logo_coordinates() by moving its declaration to
bootsplash.h and removing the static qualifier in render_bmp.c.
This allows other parts of the codebase, such as the upcoming text
rendering logic, to reuse the existing logo positioning math to
calculate destination coordinates based on alignment settings.
Change-Id: I8f8b767b093d6bc2befefdc55fe2effa38b95752
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91154
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce the infrastructure required to display an off-mode charging
notification. This is used when a device boots due to power cable
insertion but should remain in a charging state rather than booting
the full operating system.
Changes:
- Add BOOTSPLASH_OFF_MODE_CHARGING to bootsplash_type.
- Define platform_is_off_mode_charging_active() with a weak inline
fallback to allow platforms to signal off-mode charging status.
- Update bmp_logo.c to recognize "off_mode_charging.bmp" and select
it as the active logo type when charging is active.
- Modify render_bmp.c to handle layout and rendering for the charging
logo, including support for footer text if enabled.
- Ensure the rendering flow bails out early after displaying the
charging notification to prevent standard OS boot splash.
BUG=b:473480933
TEST=Able to build google/fatcat.
Change-Id: Ief4c65eaf0178ff3d736363c3e56acfe1adba14a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91106
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce CONFIG_PLATFORM_HAS_OFF_MODE_CHARGING_INDICATOR to support
rendering a dedicated splash screen when a device is in an off-mode
charging state. This provides visual feedback to the user when a
device autoboots upon power cable insertion instead of performing
a full OS boot.
Changes:
- Add Kconfig options for enabling the indicator and specifying
the logo path.
- Update Makefile.mk to include the off-mode charging BMP file
in CBFS when the feature is enabled.
- Depend on BMP_LOGO infrastructure for asset rendering.
BUG=b:473480933
TEST=Able to build google/fatcat.
Change-Id: Ib09de15ca3526bf5b10f7404dc58032d63c01e6d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The existing PLATFORM_LOW_BATTERY_SHUTDOWN_DELAY_SEC was strictly
tied to the low-battery indicator logic. This change renames and
generalizes the configuration to PLATFORM_POST_RENDER_DELAY_SEC.
By moving this out of the low-battery specific conditional block in
Kconfig, the delay can now be utilized more broadly. While it still
ensures the low-battery warning remains visible before power-off, it
can now also be used to ensure display synchronization or user
notifications are visible before passing control to the OS in normal
boot flows.
Updated Intel common reset logic to utilize the renamed config.
BUG=b:473480933
TEST=Verified that low-battery shutdown still respects the 5-second
default delay on target hardware.
Change-Id: I0277ea278fb299499f6eab2be983761a8f6ba536
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91104
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A later patch changes the .config file which we use for our tests.
However that causes the PLATFORM_USES_FSP2_0 option to be enabled, which
in turn causes build errors in our tests, because the function is
obviously not defined in our tests. Create a stub function of sorts like
we do for other coreboot table entries.
It also moves the declaration of the `lb_string_platform_blob_version`
function to coreboot_tables.h, since it doesn't belong in the FSP header
file. Because of that we can also remove the
`if (CONFIG_PLATFORM_USES_FSP2_0)`
check, which makes the code a bit cleaner.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I7721dfe4d287b2274a383bb7e5337b85a0f3f148
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
fwupd checks SMBIOS Type 0 BIOS Characteristics Extension Byte 2 bit 3
(UEFI Specification Supported) when deciding if UEFI capsule updates are
supported.
Set the flag when coreboot is built with the EDK2 payload.
Change-Id: I4d24deeca88cde5411225f8d113704f5a04e8a34
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Rename `fill_lb_framebuffer` to `get_lb_framebuffer` to better
reflect that it returns framebuffer information.
The new `get_lb_framebuffer` returns a constant pointer to the
framebuffer structure instead of filling a provided structure.
This simplifies the API and avoids an unnecessary memory copy.
The file `edid_fill_fb.c` is renamed to `framebuffer_info.c`
to better match the function it now contains.
Call sites in `coreboot_table.c` and `render_bmp.c` are
updated to use the new API.
TEST=emerge-tanjiro coreboot; check the FW logo is correctly drawn.
BUG=b:319511268
Change-Id: I8d7b20a0524b6bc9fff9e6461fa0c253345df790
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90725
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
On AMD server systems there are multiple PCI root bridges. The root
bridge scanning in UEFI Payload is not sufficient to detect the
memory and I/O apertures properly. For example on Turin system, the
I/O aperture on the first root bridge containing the FCH may not
have any I/O resources detected on the PCI devices. This results in
the I/O decoding to be disabled on the root bridge, effectively
breaking the I/O based serial ports, e.g. on Super I/Os and BMCs.
Add new CBMEM ID to report the PCI root bridge aperture information
to the payload. The intention is to use the Universal Payload PCI Root
Bridges Info HOB that is already supported in the UEFI Payload. The HOB
will take priority over the root bridge scanning and properly report
the apertures of the PCI root bridges on AMD system.
Change-Id: If7f7dc6710f389884adfd292bc5ce77e0c37766f
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Promote the condition where new_tag equals from_tag from a runtime error
to an assertion, indicating it as a critical programming error that
should not occur.
Change-Id: I1fe93b7ee0593d27f70ab3702ad4feae85857ea3
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90678
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit removes the forward declaration of the static function
`bootmem_range_string` by reordering the definition of
`bootmem_range_string` and the `type_strings` array.
Change-Id: I533660cd06f64011b861656b729eadee07803bf0
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Separating the bootblock into two copies (in BOOTBLOCK and TOPSWAP fmap
regions) breaks the CBFS verification as TSPI CRTM knows nothing about
the new regions and looks for bootblock in a hard-coded COREBOOT fmap
region.
Introduce and use cbfs_unverified_area_type_alloc() which is an
extension of cbfs_unverified_area_alloc(), very similar to how
cbfs_ro_type_map() is an extension of cbfs_ro_map(). This allows to
specify a region of the bootblock file and skip verification because
bootblock serves as a container of hashes and is not verified itself.
The branching is done on the state of RTC BUC to always use the current
bootblock. Somewhat confusingly, the measurement always uses BOOTBLOCK
region because with active Top Swap that's the way to access a
memory-mapped TOPSWAP region.
Makefile.mk now verifies both COREBOOT and COREBOOT_TS regions.
cbfstool needed a few updates as well:
- recognize both "BOOTBLOCK" and "TOPSWAP" regions
- recognize both "COREBOOT" and "COREBOOT_TS" regions
- reset metadata cache before processing each region as cache may now
be invalid
SMM doesn't link with vboot functions, so cbfs_file_hash_mismatch() has
to skip verification in SMM due to the use of CMOS options backend.
This is a part of the bootblock redundancy feature proposed
on the mailing list:
https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/
Tested by successfully booting into Protectli VP6670 with Top Swap and
CBFS Verification features enabled and Top Swap state being toggled.
Change-Id: Ia75e714ae84d8c0ae09b27495e3056313b109999
Signed-off-by: Filip Gołaś <filip.golas@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89691
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds the option to compress ramstage and payloads with zstd.
zstd compressed ramstages are typically +5% bigger than lzma compressed
ramstages. The decompressor .text section grows by 20KiB and the
decompressor needs 16KiB more heap than the lzma decompressor.
To use less heap inside the zstd decompressor the build time define
ZSTD_DECODER_INTERNAL_BUFFER is used.
Quote:
The build macro `ZSTD_DECODER_INTERNAL_BUFFER` can be set to control
the amount of extra memory used during decompression to store
literals. This defaults to 64kB. Reducing this value reduces the
memory footprint of `ZSTD_DCtx` decompression contexts, but might
also result in a small decompression speed cost
TEST=Booted on Lenovo X220 with zstd ramstage showed no disadvantage
over a bigger internal buffer used.
TEST=Booted on Lenovo X220. The zstd decompressor is twice as fast
as the lzma decompressor.
cbmem -t shows:
- finished ZSTD decompress (ignore for x86) 79,444 (24,494)
- finished LZMA decompress (ignore for x86) 94,971 (45,545)
TEST=Booted on QEMU Q35, QEMU aarch64 virt, QEMU riscv RV64 with
zstd compressed ramstage.
Change-Id: Ic1b1f53327c598d07bd83d4391e8012d41696a16
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69893
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Define ENV_RAMSTAGE_LOADER in rules.h similar to ENV_PAYLOAD_LOADER
to simplify the current code and avoid code duplication when adding
zstd support.
Change-Id: I8c049c640b11c6f0b51e37dd2c368bb786ca9b0f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90153
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Move the xxhash lib to commonlib/bsd folder so that it can be
easily included by tools. Update use of standard headers to
allow compilation on POSIX compatible systems as well.
Use the new xxhash lib in cbfstool over the existing duplicated
xxhash lib residing in lz4/lib.
Change-Id: I21041409d5b734cecf43294dcaf3bf17531dbc15
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89682
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Armv9-A architecture introduces the Memory Tagging Extension (MTE),
which uses a dedicated memory region for tag storage.
This patch adds a new memory type, BM_MEM_TAG, to allow for the proper
accounting and reservation of this memory region. This ensures that the
payload, e.g. depthcharge, can correctly identify and utilize the tag
storage area.
BUG=b:438666196
Change-Id: I2f6d2b3c2c1a8e1f0e9b2c3d4e5f6a7b8c9d0e1f
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This patch introduces a new function, bootmem_add_range_from, which
allows adding a memory range of a specific type only if it is carved
out from a range of another specific type. This is useful for cases
where memory needs to be allocated from a pre-defined region.
The function checks if the target range is fully contained within a
range of `from_tag` before marking it as `new_tag`. Error reporting
is included to log cases where the allocation is not possible.
BUG=b:438666196
Change-Id: Icfdb5ef9114572c075be6ef4e57d00151300a17a
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90469
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some silcon initialization modules may provide more detailed
information about the DIMMs, like type details or voltages.
Extend the memory_info structure with type_detail and max/min
voltage. Use the new fields when producing SMBIOS tables if their
value is non-zero. Otherwise, keep previous behavior.
Change-Id: I01ae8ea1f5a8fec53e151c040d893376c3d23be2
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89483
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If the Top Swap mechanism is enabled, after running the bootblock from
the TOP_SWAP region, boot from an updatable COREBOOT_TS FMAP region.
Having flashed the TOP_SWAP bootblock and COREBOOT_TS, this allows the
user to boot a newer version of the firmware with the ability to
revert to the previous known-good version by performing a CMOS reset.
Requires having a read-write COREBOOT_TS region in the FMAP file.
This is part of an ongoing implementation of a redundancy feature
proposed on the mailing list:
https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/
TEST=Boot Protectli VP6650, setting the attempt_slot_b flag to
different values, observing the "Booting from COREBOOT/COREBOOT_TS
region" prints correspondingly.
Change-Id: Ieadc9bfbe940cbec79eb84f16a5d622bfbb82ede
Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Extend the lb_framebuffer_flags struct to include one more bitfield
'has_dual_pipe' to indicate dual pipe support.
TEST=firmware display ok, in depthcharge with https://crrev.com/c/7129839
BRANCH=none
BUG=b:424782827
Change-Id: I082be80b4606090ed219820a407d80d9f429ea7e
Signed-off-by: Nancy Lin <nancy.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90038
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The left-up and right-up orientations were swapped. Fix it to align
with boot logo and depthcharge screen.
BUG=b:406725440
TEST=Verify all 4 panel orientation on Google/Felino.
Change-Id: Ib0d08d4b2aa697129d854c15e081c7765e542060
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The help description for `CONFIG_BMP_LOGO` in `src/lib/Kconfig` is
updated to be more generic.
Change-Id: Ic95aabe3fa3178ed5a8e4a2105364e8fb397d85f
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit introduces a new library, `vga_gfx`, to handle text
rendering on a VGA planar buffer. The new functionality supports
displaying text with various screen orientations (Normal, Left Up,
Bottom Up, and Right Up).
The key features are:
- A new public API, `render_text_to_bitmap_buffer()`, that takes a
text string, screen orientation, and buffer as input.
- Automatic text wrapping to fit the screen's effective width,
considering the specified orientation.
- The `vga_gfx.c` library is conditionally compiled for both
`romstage` and `ramstage` based on `CONFIG_VGA` and
`CONFIG_ROMSTAGE_VGA` respectively.
- Text is rendered as a 1-bit-per-pixel bitmap and then cropped
to its bounding box to optimize the output size.
- The `bootsplash.h` header file is updated with the new API
prototype and related constants.
This implementation allows for flexible text display, which is
crucial for showing user notifications on devices that may
operate in a rotated display mode.
BUG=b:406725440
TEST=Verify VGA text rotation on Google/Felino.
Change-Id: I80fcf0a3f106a44f8e4ecdeec38f54ff09f86e6f
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The multi-line `$(eval $(call ...))` for adding the default BMP logo
contained extraneous whitespace. This included a leading space before
`logo.bmp` and, more critically, a newline, tab, and non-breaking
spaces before `CONFIG_BMP_LOGO_FILE_NAME`.
This problematic whitespace was passed as part of the third argument
(`$(3)`) to the `add_bmp_logo_file_to_cbfs` macro. Inside the
macro, the deferred variable expansion `$$($(3))` would fail because it
was searching for a variable name with leading non-breaking spaces.
This resulted in the `logo.bmp-file` variable being set to an empty
string, causing a build failure when the cbfs tool tried to find the
logo file.
This commit collapses the function call onto a single line to remove
all line continuations and problematic whitespace, ensuring the
correct, clean arguments are passed to the macro.
BUG=b:444655145
TEST=Able to verify that 'logo.bmp' is added correctly to the CBFS,
and also verify the FW splash screen visible on redrix device.
Change-Id: Ia91b927dd0248909fc1c75534a7e7b00dab0fc09
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
When CONFIG_SSE is enabled use the "prefetchnta" instruction to load
the next chunk of data into the CPU cache. This only works when the
input stream is covered by an MTRR. In case the input stream is read
from the SPI ROM MMIO area it allows to keep the SPI controller
busy fetching new data, which is automatically placed into the CPU
cache, resulting in less I/O wait on the CPU side and faster
decompression.
When the input stream is not cachable the prefetch instruction has no
effect.
The SPI interfaces on the tested device runs at 100Mbit/s and the
Sandy Bridge mobile CPU has quite some work to do decompressing the
LZMA stream.
That gives the SPI controller enough time to preload data into the
cache.
The payload of 1100213 bytes is now read in 164msec, resulting in an
input bandwidth of 53MBit/s.
TEST=Booted on Lenovo X220 and used cbmem -t:
Before:
16:finished LZMA decompress (ignore for x86) 1,218,418 (210,054)
After:
16:finished LZMA decompress (ignore for x86) 1,170,949 (164,868)
Boots 46msec faster than before or 30% faster than before.
Change-Id: I3b2ed7fe0883f271553ecd1ab4191e4848ad0299
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This change introduces `LB_TAG_BOOT_MODE` to the coreboot tables to
convey platform boot information to the payload. The new `lb_boot_mode`
struct uses `enum boot_mode_t` to specify whether the device is booting
in `normal mode`, `low-battery mode` or `off-mode charging`.
This is crucial for platforms where the Application Processor (AP)
manages the charging solution, as it provides the necessary context for
the payload's charger driver. By passing this data through the coreboot
table, we avoid redundant implementation and ensure consistent battery
and charging information is available across both coreboot and the
payload.
A new weak function, `lb_add_boot_mode`, is also introduced. This
function can be overridden by platforms that require this data to add
the boot mode information to the coreboot table.
TEST=Able to build and boot google/quenbi.
Change-Id: I5aea72c02b4d6c856e2504f4007de584c59ee89f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
When get_us_since_boot() is called in pre-ram stages on x86 init
the TSC frequency. The TSC frequency is necessary to calculate
the time spent since boot.
When get_us_since_boot() is not used in pre-ram stages the function
timestamp_tick_freq_mhz() will also be dropped by the linker, thus
there's no code size increase for common code.
Will be used in the following commit in pre-ram stages.
Change-Id: I7fd9eeadf3063a629dd589498fcb957b9bd66536
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88793
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
I found a space(' ') that was probably added unintentionally
in the cbmem_run_init_hooks().
So i deleted it to make the code cleaner.
P.S. It seems that clang-format can correct issues like it but
clang-format is unusable currently. See util/lint/check-style.
And this style issue of the code hasn't been corrected since 2015.
So i decided to correct it manually for now.
Change-Id: I788047d51c1f2586c3480efc4a31848e287c5894
Signed-off-by: NyeonWoo Kim <knw0507@naver.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88325
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch fixes a bug in load_and_render_logo_to_framebuffer where the
logo_bottom_margin was only correctly applied to the NORMAL
orientations.
For other orientations, the margin was incorrectly applied, resulting
in the logo not being positioned as expected.
TEST=Able to see logo footer in alignment with the logo center while
booting google/felino.
Change-Id: Ia886ef5305166b1307fcf5b0acd12582b4b6ad80
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
DDR5 uses a Serial Presence Detect (SPD) with hub function
(SPD5 hub device) to store the SPD data. The SPD5 hub has 1024 bytes of
EEPROM (`CONFIG_DIMM_SPD_SIZE=1024`).
Ref: DDR5 SDRAM spec, JESD79-5C.01
Change-Id: Ic5e6c58f255bef86b68ce90a4f853bf4e7c7ccfe
Co-authored-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52731
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch refactors the BMP rendering logic, moving it from
drivers/intel/fsp2_0 to src/lib. This centralizes the code
responsible for rendering BMP images to the framebuffer.
Key changes:
- Move BMP rendering functions (e.g., calculate_logo_coordinates,
copy_logo_to_framebuffer) and their dependencies to
src/lib/render_bmp.c and src/lib/render_bmp.h.
- Decouple BMP definitions from UEFI headers by introducing new
coreboot-specific structures for BMP images and BLT pixels.
- Consolidate bootsplash-related declarations into bootsplash.h,
including new `fw_splash_vertical_alignment`,
`fw_splash_horizontal_alignment`, and `struct logo_config`.
- Update `soc_load_logo_by_coreboot` to use the new common
`load_and_render_logo_to_framebuffer` function and `struct
logo_config` for rendering.
- Relocate `release_logo` to `src/lib/render_bmp.c` for better
module structure.
- Update `src/lib/Makefile.mk` to include the new render_bmp.c.
This refactoring improves code organization and reusability, making
BMP rendering accessible without tight coupling to Intel-specific
driver code.
BUG=b:427387842
TEST=Verify firmware splash screen on google/fatcat.
Change-Id: I0e20ea7e44b4b3ccdb2d4aa9b6aa10ed3447ccfc
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88361
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce cbfs_preload_wait_for_all() to guarantee that all CBFS preload
contexts complete their tasks before moving forward. This function goes
through each preload context and waits for the corresponding thread to
finish by using thread_join(). If any preload thread runs into an issue,
it records an error message along with the context name.
This addition provides a synchronization point during the boot process
which platform code can leverage, typically when the storage backend
supporting asynchronous file transfer is about to be deactivated.
Change-Id: I3ee27ef2fbfdc19bd75532713966f333ad975861
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88457
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The cache buffer is expected to be aligned to CONFIG_CBFS_CACHE_ALIGN by
the mem_pool_alloc function.
Change-Id: I153a4de5ae2b8549288946d0773009d586d5c65c
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88299
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces the `SPLASH_SCREEN_FOOTER` Kconfig option,
enabling a custom footer image or logo on the firmware splash screen.
This provides an additional branding opportunity for device
manufacturers.
`soc_load_logo_by_coreboot()` now conditionally loads and renders
`footer_logo.bmp` when this option is enabled. The footer logo is
positioned at the bottom of the screen.
A new `SPLASH_SCREEN_FOOTER_LOGO_PATH` Kconfig option is added to
define the footer logo's file path. It defaults to a mainboard-specific
location. `Makefile.mk` is updated to ensure this logo is included in
the CBFS.
This additional branding is made possible by rendering bitmaps using
coreboot's native implementation (`USE_COREBOOT_FOR_BMP_RENDERING`).
FSP currently lacks the necessary callbacks to support this feature.
Currently, the OEM footer branding will appear even when the
system is booting in low-battery mode. A planned update will fix this
by exiting early from the boot process, preventing the footer from
showing and conserving power.
BUG=b:423591644
TEST=Able to display custom footer logo on boot.
Change-Id: I57f8af910e8b8f56e8a4a88f8cca6d60fad380b6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch introduces `bmp_load_logo_by_type()` to allow loading a
specific BMP logo from CBFS based on `enum bootsplash_type`.
Now, bmp_load_logo() leverages bmp_load_logo_by_type() with the
system-determined logo type. The new bmp_load_logo_by_type() function
provides a direct interface to load any specified BMP by `enum
bootsplash_type`, which is beneficial for scenarios requiring explicit
logo selection.
BUG=b:423591644
TEST=Able to build and boot google/fatcat. Ensure FW splash screen looks
proper.
Change-Id: I2473f7d48ca2d196ced89d81391cf387627a2f86
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88013
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces an enumerated type `bootsplash_type` to
differentiate between various bootsplash logos, such as
`BOOTSPLASH_LOW_BATTERY` and `BOOTSPLASH_CENTER`.
A `bootsplash_list` array is added to map these types to their
corresponding default filenames. A new function,
`bmp_get_logo_filename`, is provided to retrieve the correct logo
filename based on the specified bootsplash type. This function also
handles overriding the `BOOTSPLASH_CENTER` logo name if
`CONFIG(HAVE_CUSTOM_BMP_LOGO)` is enabled.
The `bmp_load_logo` function is updated to utilize the new
`bootsplash_type` and `bmp_get_logo_filename` to dynamically select the
appropriate logo for display. This change streamlines logo management
and improves flexibility for different boot scenarios.
BUG=b:423591644
TEST=Able to build and boot google/fatcat. FW splash screen looks
proper.
Change-Id: I882deda56b5d30bb15cc7def408c4ea479ffd6ba
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Now that we require the FMAP to start at offset 0 in the flash, we can
assume this across the entire codebase and therefore simplify it on
several ends.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ieb1a23f9c0ae8c0e1c91287d7eb6f7f0abbf0c2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86771
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
The `display_init_required` function for vboot now mandates that either
`CONFIG_VBOOT_MUST_REQUEST_DISPLAY` or
`CONFIG_VBOOT_ALWAYS_ENABLE_DISPLAY` must be enabled.
If neither of these Kconfig options is set when `CONFIG_VBOOT` is
enabled, the code will now trigger `dead_code()`. This enforces the
requirement that display initialization is explicitly requested or
always enabled when vboot is active, aligning with the intended usage
of `VB2_CONTEXT_DISPLAY_INIT`.
TEST=Able to build google/fatcat.
Change-Id: I371c0533057fb088ea15a5da6bd76173cea525aa
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit introduces a new timestamp `TS_DEVICE_INIT_CHIPS` to
specifically mark the start of the `dev_initialize_chips()` function.
Previously, the `TS_DEVICE_ENUMERATE` timestamp was incorrectly
associated with the `bs_dev_init_chips` function.
This patch corrects this by:
- Adding the `TS_DEVICE_INIT_CHIPS` enum and name definition.
- Updating `bs_dev_init_chips` in `src/lib/hardwaremain.c` to use
`TS_DEVICE_INIT_CHIPS`.
- Moving the `TS_DEVICE_ENUMERATE` timestamp addition to the
`bs_dev_enumerate` function where device enumeration actually begins.
This change provides a more accurate and meaningful timestamp for the
early chipset initialization phase.
TEST=Able to build and boot google/fatcat.
```
971:loading FSP-S 836,277 (10,658)
17:starting LZ4 decompress (ignore for x86) 847,297 (11,019)
18:finished LZ4 decompress (ignore for x86) 847,376 (79)
30:early chipset initialization 854,579 (7,203)
17:starting LZ4 decompress (ignore for x86) 863,483 (8,903)
18:finished LZ4 decompress (ignore for x86) 863,490 (6)
17:starting LZ4 decompress (ignore for x86) 875,196 (11,705)
18:finished LZ4 decompress (ignore for x86) 875,237 (41)
954:calling FspSiliconInit 875,344 (107)
955:returning from FspSiliconInit 942,740 (67,396)
962:calling FspMultiPhaseSiInit 942,744 (4)
963:returning from FspMultiPhaseSiInit 1,081,355 (138,610)
31:device enumeration 1,081,708 (352)
40:device configuration 1,085,721 (4,013)
50:device enable 1,091,517 (5,795)
```
Change-Id: Ib6860901c6b1528ec5098fc93240c6e65777642b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
The arch include files are overshadowed by PSP verstage include files.
The reason is that psp_verstage implements its own set of inb() and
outb() functions, which use a runtime configurable IO base address
instead of a built time constant.
But this works at the moment only because of the order in which the
include files are added. Since that is very error prone, this patch
introduces another solution to the problem.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I16fa4a4cb5168024aaef30119e9aa8a34dbaacbe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The FW_CONFIG_SOURCE_CBFS option serves as a backup for
FW_CONFIG_SOURCE_CHROMEEC_CBI, utilizing variables stored in CBFS.
When using ChromeEC CBI as the firmware configuration source,
changes to fw_config values can be made without updating the firmware
image. However, using CBFS as the configuration source requires
resigning the firmware because the current implementation reads from
the RW firmware region (FW_MAIN_A/B), necessitating resigning for
updates. To avoid this step, the code should be modified to use the
RO CBFS for fw_config values instead of the RW (Read-Write) CBFS.
TEST:
1. Add FW_CONFIG_SOURCE_CBFS in board Kconfig and build image
2. Modify fw_config value by cbfstool with built image
3. flash and boot up system
4. Check updated fw_config value
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I4710a1043fe75888d2dcaee98c6957e6bd639be9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86943
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Use already defined macros in `spd.h`, ddr3.h`and `ddr4.h`.
TEST=Built google/cyan (Cyan) with BUILD_TIMELESS=1, no change in output
ROM.
Change-Id: I727aa38236ad97f9c529389fdb7d7d11c1db08d0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82314
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
