The mipi_cmd_func_t callback for mipi_panel_parse_init_commands()
currently doesn't support passing additional data for storing context.
Therefore user code would need to store any extra data in global
variables. For example, in the upcoming DSI dual channel support for
MediaTek platforms, the callback needs to know whether the MIPI panel
supports dual channel or not. To support that use case, pass an extra
`user_data` argument to mipi_cmd_func_t.
BUG=b:424782827
TEST=util/abuild/abuild -x -t GOOGLE_SAPPHIRE -a
BRANCH=none
Change-Id: Id5d7b168cdcadfe8d8435c29d7e855a535815057
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
The previous default size of 256KB provided for only 64KB of actual
space for EFI variables, and after accounting for fragmentation, did
not provide enough free space for applying updates, such as for the
UEFI revocation database (DBX). Increasing it to 512KB allows for
192KB space for variables, and allows the UEFI DBX to be updated
properly via fwupd.
TEST=build/boot google/drobit, verify UEFI DBX able to be successfully
updated via fwupd.
Change-Id: I8d6a2051f3ad50117d41cec2bbbe3aaafa7e65c2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90287
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The SSDT contains:
CreateByteField (PPOP, Local0, TPPF)
However, CreateByteField requires the source argument to be
(Buffer | String | Integer). PPOP is an OperationRegion, so
iasl correctly reports:
Error 6058 - Invalid type ([Region] found)
Per ACPI spec, OperationRegions must use CreateField rather than
CreateByteField. Replace the AML emission with:
CreateField (PPOP, Local0 * 8, 8, TPPF)
This reads one byte at an arbitrary offset inside the PPI
OpRegion and is fully standards-compliant. This isn't a
functional change, just "correct".
Test=boot starbook_mtl, verify iasl can decompile and recompile
SSDT and TPM is still operational.
Change-Id: If80bb5bf69562f8b904c1b315e95a0b5627efbc4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This update enhances the Intel touch driver by incorporating support for
newly added _DSD entries specific to I2C devices. The enhancements
include:
- Adding new entries in the I2C _DSD to enable configurations for
maximum frame size and interrupt delay settings.
- Introducing device-specific interrupt delay settings tailored for
Hynitron devices.
These changes ensure improved configurability and performance tuning for
supported devices. It is crucial to use this update with an operating
system that includes corresponding changes for this new support.
ATTENTION: This change requires a THC driver fix. If the OS does not
have the driver fix, please use LPSS I2C or disable the touchscreen
and touchpad. For instance, on the Google Fatcat board, use the
following CBI fw_config options:
TOUCHSCREEN field: TOUCHSCREEN_LPSS_I2C or TOUCHSCREEN_NONE
TOUCHPAD field: TOUCHPAD_LPSS_I2C or TOUCHPAD_NONE
BUG=none
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Iaab8329c97247161395d203a5efa92c053acb3a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89214
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kim, Kyoung Il <kyoung.il.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The breaks for `if` and `else` are inconsistent; remove all breaks for
these.
Change-Id: Ie76f38387fd5ef330b432c0462cb1101571c73db
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90286
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The existing brightness level fallback logic duplicated the default
backlight value by hardcoding BRLV to 100% (0x64). This caused divergence
whenever a platform defined a different default brightness through BRIG[0].
This change removes the duplicated default and replaces it with a cached
brightness mechanism using BRVA (valid flag) and BRLV (cached level).
The firmware now:
- Caches the last brightness level exposed to the OS.
- Uses the cached level during early boot/resume when the OpRegion
(BCLM/BCLV) is not yet initialized.
- Falls back to BRIG[0] only when no cached brightness exists.
- Preserves the existing replay-detection logic to keep firmware and OS
brightness state aligned once the graphics driver is active.
This ensures consistent brightness reporting, avoids incorrect 0% fallback
values, and respects board-specific BRIG defaults.
No functional changes occur once the graphics driver has initialized the
OpRegion; the improvement only affects early boot/resume behavior and
eliminates duplicated platform policy.
Change-Id: I651dfd30aa0c283b4e0659e5d19051e1b58204fe
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Since the structs are the same, we may as well use the ones directly
from the driver (since it implements the standard anyway).
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I44116e5e977029c37e1bf9b9d8ce8d6c022b5b0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The EFI variable store driver (efivars.c) and option backend
(option.c) require EDK2 headers which are x86-specific and not
available in ARM verstage. Use 'all_x86-' instead of 'all-' to
exclude verstage while keeping other x86 stages and SMM.
TEST=build google/dewatt with CFR enabled
Change-Id: I6d0955423cb55658725dfa3025b2118736f5e63b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90296
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The OS replays _BCM requests while the graphics driver is
still reinitializing, so hardware brightness can diverge
from what we cached in BRLV. Reapply the cached level once
the OpRegion is ready to keep firmware and OS state aligned.
Change-Id: I2e6ed0936b2e74f55a2c760e7f4fcf56a2e02c53
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Our 18-entry BRIG table advertised is only a handful of steps and
identical AC/DC defaults, so after S3, the OS falls back to the
default index if the the cached entry doesn't match.
Populate BRIG with the full 0–100 ladder so every cached index
corresponds to an actual entry.
Change-Id: I319cf3a0ced3bf6021f9e768f0e9bb5529b12ed5
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89987
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Cache the brightness level requested via _BCM and return it from XBQC
while the IGD OpRegion registers are still zeroed during S3 resume.
Once BCLM is valid we refresh the cache with the hardware reading.
This keeps _BQC from reporting zero after resume.
Change-Id: I3f06c9cf6529da6d634d7b0368f0c88b468f0c45
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Remove the (unused) disable_ssdb_defaults field and its usage. SSDB
defaults should always be applied to ensure proper camera sensor
configuration. This simplifies the code and ensures consistent behavior
across all camera sensor configurations.
TEST=tested with rest of patch train
Change-Id: I3bc00cdd28ace925b44712a17dec07f7f2b8c97a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Set SSDB version and card type default values, as both fields
are required by both Linux and Windows MIPI camera drivers.
TEST=tested with rest of patch train
Change-Id: Ia43bc61caef427a86883a6295af1606eac00229f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Remove the use_pld and disable_pld_defaults flags and always generate
the Physical Location Descriptor (PLD) for camera sensor devices. PLD
is required for proper camera enumeration and identification in modern
ACPI implementations, so making it optional was incorrect.
Changes:
- Remove use_pld field: PLD generation is now always enabled
- Remove disable_pld_defaults field: PLD defaults are always applied
- Always call apply_pld_defaults() and acpigen_write_pld()
TEST=tested with rest of patch train
Change-Id: Ifd408f32a4feaf9728913dd150d1cb3e7b1c3c60
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Add comments for the tail of `struct intel_ssdb`, naming the camera
position, voltage rail, PPR, flash, PHY, lane, and external MCLK fields
instead of treating them as an opaque reserved block. Keeps the struct
aligned with the ACPI blob while making each byte’s meaning explicit.
Change-Id: Id9ae2bf77e901ef0f88b6f51985b59d41c5529d9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Switch the `sensor_card_sku` field in `struct intel_ssdb` from a raw
byte to the new `sensor_sku_info` bitfield wrapper so callers can access
the vendor/card type flags symbolically. Field size stays the same, so
layout and behavior are unchanged.
Change-Id: I85ecbbec1a749c07e4d83d953d47d76854447cb1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Introduce enums covering the SSDB ROM/VCM types, orientation, control
logic, camera position, voltage rails, PHY config, MCLK source, SKU
vendor, and SKU card type fields, plus a packed helper for the SKU
bitfield. This replaces magic values with named constants ahead of
further SSDB work without changing behaviour.
Change-Id: Iacc1a844528e2427c9f4ca8fcebe338fb6c1bac4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90187
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce `platform_subtype` constants for the SSDB `platform_sub`
field, matching the legacy FFD/CHT1/CHT2 values plus an unknown
default.
Change-Id: Ib705252b089d161a7addc372d05e5062307bfb21
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Retitle the SSDB flash-support enum to `flash_support`, aligning its
name with the field in the struct and the spec. Also keep the existing
values and clarify the default case comment.
Change-Id: I49d825cb44d7f8784350e29e8b2b5a0772549f56
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90185
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rename `intel_camera_platform_type` to `platform_type` and populate it
using the available values from the Intel Camera DDK available on
Windows Update and slimbootloader.
Change-Id: I7c40e29dbf71caf7b655e8f2e5b4be7cc6970194
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90184
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a static assert ensuring `struct ssdb` stays 0x6C bytes, matching
the sensor descriptor in ACPI. This guards future edits from drifting
away from the documented layout without changing runtime behavior.
Change-Id: I2b4dfb86494d13525cbc6e6de4573ceb36f0b482
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90183
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reflow the multiline comments in `ssdb.h` to 100 columns.
While this slightly exceeds the 96 column recommended limit in the
coding style guide, the overall effect improves rather than reduces
readability.
Change-Id: I5b98d48ea5a99e38eb3472dfd24be434433857cc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Move the sensor SSDB struct and enums out of `chip.h` and into a new
`ssdb.h`. This keeps the chip interface header lean while providing a
dedicated spot for the additional SSDB field descriptors coming in
follow-up changes. No functional impact.
Change-Id: Ifb2dddb886f0123b1dfd059400dcacd75174fb6c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90181
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When BOX3.XBCM fails we currently fall back to LEGA.XBCM, which writes
directly to the IGD PWM registers. During S3 resume those registers are
still reset by the graphics driver, so AML stores a zero duty cycle and
the panel stays dark. This leads to having some other event needed to
wake the panel (i.e. key press).
Only invoke the legacy path after BCLM is initialized, matching when the
driver has reprogrammed the PWM registers and preventing firmware from
touching them while the driver is still restoring them.
Test=Enter and exit S3 on starbook_mtl, verify that the display turns on and stays on, instead of on -> off -> on.
Change-Id: I664d296372feef9de5c4f57428422328c4e33110
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89985
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The FSP structs are usually typedefs and are also used like that across
the tree.
In order to make this file usable for code inside our tree
(specifically AMD) change it to typedefs.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ie799e0116997ba559b990a9b3a2038fea852d8ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
There is one too many `endif` in this file. The only reason why jenkins
never complained is because this is apparently never included (and
therefore never compiled) by any code/mainboard in our tree.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Id68d91d5c5365000fc97815d184d48f4b71bcb35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Add driver to read 'hwid' file from CBFS and use it for SMBIOS product
name. Processes the ChromeOS-format HWID string by removing prefix
after colon, trimming whitespace, and extracting base name before
any hyphen/space. Returned string is normalized to have the first
character/letter capitalized, and the rest lower case. If no HWID file
is found in CBFS, the fallback is CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME.
This driver is intended to allow ChromeOS devices running upstream
coreboot to persist their board's unique HWID and use it as the SMBIOS
board name, but it is not limited to that function.
TEST=tested in MrChromebox downstream. Multiple devices which use the
same ChromeOS board but differ in HWID can use the same firmware image
and still be properly identified.
Change-Id: I1af1df4c79858d23ef71400abe72f41eec6c25c6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
We used to put SMBIOS header and other data before VPD. That is not the
case anymore. New device will write the VPD starting at 0 instead of
0x600. Search VPD at 0x0 to support this.
TEST=build and boot google/geralt. VPD is found both at 0 and at 0x600.
Change-Id: I7072f7c646b6b55d11bc06dba5674828246fa1d0
Signed-off-by: Jian-Jia Su <jjsu@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add a new Kconfig option, FSP_VGA_MODE12_MONOCHROME, to allow the
system to use a 1-bit-per-pixel (1bpp) planar VGA buffer during FSP
initialization instead of the standard 4bpp buffer. This is useful
in romstage where every byte is critical.
When this option is enabled, the FSP is expected to handle the
internal replication of the 1bpp data across the other three
color planes to render the monochrome image.
Key changes:
- Introduce FSP_VGA_MODE12_MONOCHROME Kconfig option.
- Automatically select FSP_VGA_MODE12 when the monochrome option is
used.
- Set FSP_VGA_MODE12_BPP to 0x1 when FSP_VGA_MODE12_MONOCHROME is
selected.
BUG=b:406725440
TEST=Verify VGA text rotation on Google/Felino.
Change-Id: Ie77c40025c13e52188439fffedc834c26338bfe3
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
When updating clang to version 21.1.5, we now get the following error
when compiling the CFR code.
```
src/drivers/option/cfr.c:287:19: error: default initialization of an
object of type 'struct sm_object' with const member leaves the object uninitialized
[-Werror,-Wdefault-const-init-field-unsafe]
287 | struct sm_object sm_obj_copy;
```
In this specific case its actually not an issue, but initialize the
variable from the start to avoid the error and arguably make the code
easier to read.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ib0b22e20a7482ab29d997a3e3c3bec4a1db1a4f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89958
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is no reason I can think to also pass the old object into the
constructor considering that the new objects contains the exact same
contents during that call (it's copied over a few lines above).
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Idd5b34134b6064c19266448b551248eb29e097fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89957
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add ACPI power state methods (_PS0, _PS3, _S0W, _S3D) to the GFX0
device definition to fix VIDEO_TDR_FAILURE 0x116 errors when
resuming from S3 sleep under Windows on modern Intel platforms
(TGL and newer).
Windows requires these methods to properly manage GPU power states
during sleep/resume cycles. Without them, Windows cannot determine
the correct power state transitions, leading to display driver
timeouts on resume.
The methods are implemented as no-ops since integrated graphics
power is managed by the platform, but Windows needs the method
definitions to properly initialize and restore the GPU after S3
resume.
TEST=build/boot starlabs/starlite_adl, verify S3 resume from
Windows works properly without a VIDEO_TDR_FAILURE BSOD.
Change-Id: Ib3f8060dee3281c2281d4e719be9aff9e0239b49
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90013
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently we may return an undefined pointer called
`none_driver_config` since stack variables are not by default
initialized to 0/NULL.
This also causes an issue when updating to a clang version 21.1.5 from
version 18.1.8, since it complains about this very issue.
returning NULL is fine, since the macros in this file actually depend on
it to figure out where to get the config from.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I7b719ca9fd41409375f635b1dcddbc5796b48fe7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Enables correct identification of boards using tas2563 speaker amplifier
by SOF Windows drivers.
BUG=b:451935496
TEST=Build and boot to Android16 with Linux 6.12.52 and check tas2563 audio driver was probed successful.
Change-Id: I7dd0276a44ebb9b0712589c28ac017bff1ed5b1a
Signed-off-by: David Lin <david.lin@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89878
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This driver uses the ACPI Device Property interface to generate
the required parameters into the _DSD table format expected by
the kernel.
This was tested on the fatcat/variants/ruby mainboard to ensure
that the SSDT contained the equivalent parameters that are provided
by the current DSDT object.
BUG=b:451935496
TEST=Build and boot to Android16 with Linux 6.12.52 and check tas2563 audio driver was probed successful.
Change-Id: I801ef13937078ca9cfcd3610b1aa8aaedbaf1cf1
Signed-off-by: David Lin <david.lin@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Chiang, Mac <mac.chiang@intel.com>
Add a mechanism for mainboards to override default values of CFR
objects defined in SoC or common code without duplicating object
metadata.
Mainboards can now declare a simple override table mapping option
names to new default values:
const struct cfr_default_override mb_cfr_overrides[] = {
CFR_OVERRIDE_BOOL("s0ix_enable", false),
CFR_OVERRIDE_ENUM("pciexp_aspm", ASPM_DISABLE),
CFR_OVERRIDE_END
};
The CFR backend checks this table when writing options and uses the
override value if one exists. All other metadata (name, help text,
enum values, flags) comes from the original object.
Change-Id: Ifb3da90d605f2799bf0207ff58d69bee3415ccc2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89933
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds new Kconfig options and a code snippet to support
VGA mode 12 within the FSP (Firmware Support Package) 2.0. The
changes allow platforms to select VGA mode 12 and configure it.
The key features are:
- Introduces `FSP_VGA_MODE12` to enable VGA mode 12 support.
- A new `FSP_VGA_MODE12_BPP` option defines the bits per pixel,
defaulting to 4 for color mode.
- A bitmap buffer is allocated on the stack and supplied to FSP
based on the configured bits per pixel.
BUG=b:406725440
TEST=Verify VGA text rotation on Google/Felino.
Change-Id: Iaa3a64b7c8c735d8329b3596f4be315871bc7fa4
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Commit ddf5987c1e ("drivers/mipi: Add support for
TM_TL121BVMS07_00C panel") (CB:89216) added support for the
TM_TL121BVMS07_00C panel, but the screen was not functional.
Decrease the pixel clock from 4,400,560 Hz to 264,355 Hz to match the
actual panel timing specification. Also, the panel uses C-PHY interface,
so enable the `PANEL_FLAG_CPHY` flag accordingly.
Datasheet: Preliminary+specification+TL121BVMS07+-00+V01+20250721.pdf
BUG=b:428854543
TEST=build and check firmware screen.
BRANCH=skywalker
Change-Id: I88fa5215d7596926aa95a58ae91dd6ade793388b
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89568
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change the I2C connection speed type from uint32_t to the i2c_speed
enum type for better type safety and code consistency. While the
i2c_speed enum values correspond to actual speed values in Hz, using the
enum provides clearer intent and prevents invalid speed values.
Additionally, add logic to use standard I2C speed (100 kHz) when no
recommended or required speed is specified in the device tree, SoC
configuration, or device settings.
BUG=none
TEST=Boot Fatcat board to OS and verify correct I2C speed assignments in
'DSPD' Name object under THC device from SSDT. Confirm touch devices
operate at expected speeds.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ie01693544bebf9f748d16606fc13f39fe4069b03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89649
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This change adds a null pointer check to ensure that the SoC-specific
function to retrieve I2C bus speed is properly mapped before attempting
to call it. Without this check, systems may crash during boot when the
function pointer is not initialized. The issue occurs when the
touchscreen or touchpad is configured to use THC-I2C via CBI fw_config,
but the underlying SoC doesn't provide the required I2C speed function
implementation.
BUG=none
TEST=Boot Fatcat board to OS with CBI fw_config selecting touchscreen or
touchpad using THC-I2C. Verify no crash occurs during boot and touch
devices function properly.
Change-Id: Ib982f4435aa506f2b9203f81140366addc6559f3
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
CS42L43 contains a range of optional properties which control the
behaviour of jack and accessory detect, and are added here.
These properties are documented in the Linux kernel source code, in the
file:
linux/Documentation/devicetree/bindings/sound/cirrus,cs42l43.yaml
which contains names, descriptions, valid and default values.
Being optional, these properties will be ignored if not specified.
Change-Id: I53fbed81df9157022384d5879c9d9ed351641ab5
Signed-off-by: Maciej Strozek <mstrozek@opensource.cirrus.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Unlike already implemented Keyboard Controller Style (KCS) interface
Block Transfer interface is not byte-oriented and implies that device is
capable of buffering a command before processing it. Another difference
is that polling can be replaced with interrupts, though this isn't used
by this implementation.
More details can be found in "Intelligent Platform Management Interface
Specification", v2.0, Rev. 1.1:
https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/ipmi-intelligent-platform-mgt-interface-spec-2nd-gen-v2-0-spec-update.pdf
This was initially tested on Talos II (OpenPower platform) by Raptor
Computing Systems. Later versions were tested using QEMU and ipmi_sim
from OpenIPMI project as well as QEMU's builtin BMC simulator.
Change-Id: Idb67972d1c38bbae04c7b4de3405350c229a05b9
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67057
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Complies with the Multi-Processor (MP) service as defined by the
EFI_MP_SERVICES_PROTOCOL.GetProcessorInfo() in the Platform
Initialization Specification 1.7. If bit 24 (CPU_V2_EXTENDED_TOPOLOGY)
is set in ProcessorId, GetProcessorInfo() must populate the
EFI_CPU_PHYSICAL_LOCATION2 data structure.
TEST=FSP using PI 1.7 GetProcessorInfo() is able to retrieve the
information instead of receiving an EFI_NOT_FOUND error.
Change-Id: If4d473901c8de02b3d6cef44f5481a1864f14d65
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89462
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Enhancements have been made to the Intel touch driver, including support
for Google touchscreen devices, ELAN9006 and ELAN6918. The update
also includes device-specific configuration changes for both I2C and SPI
interfaces.
Key improvements include:
- Google Touchscreen support integration for ELAN9006 (SPI) and ELAN6918
(I2C).
- Specification of recommended connection speeds for supported devices.
- Removal of an unnecessary 100ms delay in the SPI _RST method.
- Addition of a function to map the System on Chip's (SoC) I2C speed
frequency.
- Improved device-specific connection speed settings for both I2C and
SPI interfaces.
These changes aim to improve the driver’s compatibility and efficiency
when interacting with the newly supported devices.
BUG=none
TEST=Test the updated driver on devices using ELAN9006 and ELAN6918 to
verify improved responsiveness and correct device initialization.
Confirm that connection speeds are set as recommended and check the
absence of the previously unnecessary delay in SPI operations from the
SSDT.
Change-Id: Ie35de90ece44101aea008d13d19e12873cdc09bf
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This patch extracts the implementation responsible for retrieving DIMM
information from the FSP HOBs and centralizes it within the common FSP
driver code.
This ensures that each SoC layer does not duplicate the logic for
parsing memory-related data. The primary goal is to rely on the
common FSP driver code for retrieving memory information.
The only SoC-specific implementation that remains is limited to
handling dependencies related to FSP UPD or header differences across
SoC generations.
TEST=Able to build and boot google/kinmen. Verify the memory related
information is proper as part of the SMBIOS table.
Change-Id: Ic3741a248bb1fe9420c784d51fbf459a30f8c42f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89494
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to QEMU docs/specs/fw_cfg.rst, the selector and data register
offsets of Arm & RISCV should be 0x8 and 0x0. Besides, the selector
register should be in big-endian when using MMIO access.
TEST=build and run successfully on QEMU rvvirt machine. Using command
"qemu-system-riscv64 -machine virt -bios build/coreboot.rom -nographic
-drive if=pflash,file=./build/coreboot.rom,format=raw".
Change-Id: I1c4d40a4dbcac4067a7c69ba916e6ff0a21cdcb6
Signed-off-by: Dong Wei <weidong.wd@bytedance.com>
Signed-off-by: Ziang Wang <wangziang.ok@bytedance.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
