- Code to initialize sdram from C on the l440gx
- cache as ram code fro the p6 it works except conflict misses occur
with addresses that are not cached so writing to ram does not work.
Which makes it to brittle to count on.
- Initial implementation of a fallback booting scheme where we can
have two copies of linuxbios in rom at once.
- Movement of 32 bit entry code from entry16.inc to entry32.inc
- Update of all config files so they now also include entry32.inc
- Fix for start_stop.c & entry16.inc so I can fairly arbitrarily relocate
the 16bit entry code in SMP.
- A small number of fixes for warnings
- VIA 686 cleanups from the A7M code (it now works in a different pci slot).
- Update of assembly printing routines to use the debug levels:
TTYS0_TX_CHAR now becomes CONSOLE_<LEVEL>_TX_CHAR.
It's more verbose but now the controls are the same as with the C code.
- Break off of loglevel.h from printk.h. loglevel.h is safe for both
the assembly routines and the C code to include.
- Next round of commits for the supermicro p4dc6
- SMP setup updates (Rons board is broken)
I now allow the other SMP processors to report their existence.
I really need to add a minimum time to run but that hasn't happened yet.
- SMP per motherboard table of apicids, as the assumption that they
would always be 0 & 1 with only two cpus fails.
- RDRAM setup updates. The code isn't done but it now works on more
than one board at a time.
- More cacheram work. Minor bug fixes and some macros to use it from C.
- Entry point changes so we no longer have to jump over our gdt.
- Added/Audited the cpufixup for the i786
- IDE intialization for the 82801 ich2 chip.
This also includes a bunch of my pending work including
- Updated serial code so we can compile in different serial port speeds
- Updates to the build system so that:
- Makefile.settings holds all of the settings of the config variables
- ldoptions and cpuflags are generated automatically with perl scripts
- src/config/Config holds all of the architecture neutral make file settings
- Initial work on the P4 including how to use cache as ram
- Update to the ioapic code for the P4 because it delivers irqs on the system
bus instead of an out of band bus
- Updated version of printf that doesn't need an intermediate buffer
- logbuf_subr now handles the case when we want to use a log buffer
- video_subr handles the preliminary code for writing to a video device.
- Pending changes for the L440GX are merged in as well (hopefully I haven't
messed then up since they were written).
Add rule for ldscript.ld
printk.h
Fix typo it should be printk_alert not printk_alart...
NLBConfig.py
- Removed some dead code
- Modified mainboardinit and ldscript to act like my recently modified
object command and take as a suffix a config option that must be
set to one for them to work.
- No longer generate ldscript.ld instead generate ldoptions and
the variable LDSUBSCRIPTS-1.
make.base -- renamed OBJECTS to OBJECTS-1 to allow conditional compilation of objects
ldscript.base -- realized that assignemnts to the location counter inside of sections
are relative to their start so simplfied the code
pirq_routing.h -- includeded types.h so we don't have suprises
hardwaremain.c -- unconditionally included arch/smp/mpsec.h
arch/i386/smp/Config introduced conitional on the compilation objects into
the compilation process
ioapic.c -- removed (now) unneeded ifdef around this file
mpsec.c -- removed (now) unneeded ifdef around this file
cpu/cpufixup.h -- Fix typo in the case when no cpufixup is needed.
parts/framebuffer.h -- Added a missing semicolon.
smp/atomic.h -- renamed second atmoic_inc to atomic_dec oops.
tyan/guinnes/Config -- reordered the options so they are grouped a little
better and said mptable.o is dependent on HAVE_MP_TABLE
tyan/guiness/mainboard.c -- small change for clarity.
northsouthbridge/sis/630/northbridge.c
northsouthbridge/sis/630/southbridge.c
-- Remove unused include of the now dead param.h
NLBConfig.py
-- Only include numeric options in the linker script
-- Update to handle adding a condition for when to build
objects
boot.c -- Modified to compile even with -fPIC
generic_sdram.inc -- split out generic_sdram_enable.inc -- Some chipsets
don't need that enable logic.
Added serial_fill_inbuf.c
Removed unused 440gx/param.h sis/630/param.h
Modified: make.base crt0.base ldscript.base mainboard/Config and NLBConfig.py
In NLBConfig.py added the directive mainboardinit (a variant of raminit.inc)
This allows us to remove hardcodes in crt0.S updated every mainboard/Config to
reflect the current state of the hardcodes, and the split of generic_sdram.inc
In crt0.S we should have the bare minimum code in assembly needed to get to C code.
mkrom is no longer needed.
newpci.c has some new functions. asus config is fixed for i386 stuff.
NLBconfig has a new command (nsuperio) and will take arch, mainboard, or
target as the first command. sis 950 superio has changes for the new
superio model
Added set_initrd() to params.h and params.c.
Added PRINTK macro and KERN_SPEW to printk.h.
Changed fill_inbuf.c to accept zkernel_start and zknernel_mask as
variables that can be set by linuxbiosmain().
Changed linuxbiosmain() to allow custom code to modify some parameters
such as where the kernel image is located in ROM, the initrd parameters
and the command line.
Change most of the DBG's in newpci.c to PRINTK(KERN_SPEW... This was
the worst offender when DEBUG was defined. Some of it was changed to
KERN_DEBUG.
There are no new files this time, however,
freebios-010214.orig/src/superio/SMC/fdc37n769/superio.inc
remains and needs to be deleted and then 'cvs rm'.
None of these changes should break any other code. The same
ZKERNEL_START, ZKERNEL_MASK and CMD_LINE defines are still used, but
are now all used in linuxbiosmain() and used to initialize variables
that can later be changed rather than used directly.
These changes allow me to choose between two kernel images, optionally
use an initrd image, load the initrd image and set the kernel command
line as needed.
