pci_ids.h --- Added new ids.
boot.c -- Modified to compile even with -fPIC
generic_sdram.inc -- split out generic_sdram_enable.inc -- Some chipsets
don't need that enable logic.
Added serial_fill_inbuf.c
Removed unused 440gx/param.h sis/630/param.h
Modified: make.base crt0.base ldscript.base mainboard/Config and NLBConfig.py
In NLBConfig.py added the directive mainboardinit (a variant of raminit.inc)
This allows us to remove hardcodes in crt0.S updated every mainboard/Config to
reflect the current state of the hardcodes, and the split of generic_sdram.inc
In crt0.S we should have the bare minimum code in assembly needed to get to C code.
mkrom is no longer needed.
This commit is contained in:
Eric W. Biederman
parent
228148aa23
commit
ebccffe3d0
31 changed files with 256 additions and 150 deletions
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@ -1,9 +1,11 @@
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biosbase 0
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rambase 0x8000
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makedefine LINK = ld -T ldscript.ld -o $@ crt0.o linuxbios.a
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makedefine CPPFLAGS= -I$(TOP)/src/include -I$(TOP)/src/arch/$(ARCH)/include $(CPUFLAGS)
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makedefine CC:=gcc
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makedefine LIBGCC_FILE_NAME := $(shell $(CC) -print-libgcc-file-name)
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makedefine GCC_INC_DIR := $(shell $(CC) -print-search-dirs | sed -ne "s/install: \(.*\)\`include/gp")
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makedefine CPPFLAGS= -I$(TOP)/src/include -I$(TOP)/src/arch/$(ARCH)/include -I$(GCC_INC_DIR) $(CPUFLAGS)
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makedefine CFLAGS= $(CPU_OPT) $(CPPFLAGS) -O2 -nostdinc -nostdlib -fno-builtin -Wall
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makedefine CC=cc
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makedefine LINK = ld -T ldscript.ld -o $@ crt0.o linuxbios.a
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makerule all : linuxbios.rom ;
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makerule linuxbios.rom: linuxbios.strip makerom ; ./makerom -l0x310000 -i7 -v linuxbios.strip -o linuxbios.rom
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makerule linuxbios.strip: linuxbios ; objcopy -O binary -R .note -R .comment -S linuxbios linuxbios.strip
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@ -1,2 +1,3 @@
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dir boot
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dir lib
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dir smp
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@ -85,8 +85,12 @@ void jmp_to_elf_entry(void *entry, void *ube)
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/* Jump to kernel */
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__asm__ __volatile__(
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"pushl %0\n\t"
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"pushl %1\n\t"
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"pushl %2\n\t"
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"popl %%ebx\n\t"
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"popl %%eax\n\t"
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"ret\n\t"
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:: "g" (entry), "a"(type), "b"(ube));
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:: "g" (entry), "g"(type), "g"(ube));
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}
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@ -3,8 +3,8 @@
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*
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*/
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#include <asm.h>
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#include <intel.h>
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#include <arch/asm.h>
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#include <arch/intel.h>
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#include <pciconf.h>
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/*
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@ -24,25 +24,22 @@
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#include <cpu/p5/start32.inc>
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#include <pc80/i8259.inc>
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CRT0_PARAMETERS
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#ifdef INTEL_PPRO_MTRR
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/* Turn on mtrr for faster boot */
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#include <cpu/p6/earlymtrr.inc>
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#endif /* INTEL_PPRO_MTRR */
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/*
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* Copy data into RAM and clear the BSS. Since these segments
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* isn\'t really that big we just copy/clear using bytes, not
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* double words.
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*/
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intel_chip_post_macro(0x11) /* post 11 */
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#ifdef SERIAL_CONSOLE
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#if defined(SERIAL_CONSOLE) && defined(DEBUG)
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TTYS0_TX_STRING($str_after_ram)
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#endif /* SERIAL_CONSOLE */
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#endif /* defined(SERIAL_CONSOLE) && defined(DEBUG) */
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/* clear boot_complete flag */
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xorl %ebp, %ebp
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__main:
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/*
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* Copy data into RAM and clear the BSS. Since these segments
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* isn\'t really that big we just copy/clear using bytes, not
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* double words.
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*/
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intel_chip_post_macro(0x11) /* post 11 */
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cld /* clear direction flag */
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@ -57,10 +54,6 @@ CRT0_PARAMETERS
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.Lnodata:
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intel_chip_post_macro(0x12) /* post 12 */
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#ifdef SERIAL_CONSOLE
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TTYS0_TX_STRING($str_after_ram)
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#endif /* SERIAL_CONSOLE */
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/** clear stack */
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leal EXT(_stack), %edi
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movl $EXT(_estack), %ecx
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@ -79,25 +72,44 @@ CRT0_PARAMETERS
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stosb
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.Lnobss:
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/*
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* Now we are finished. Memory is up, data is copied and
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* bss is cleared. Now we call the main routine and
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* let it do the rest.
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*/
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intel_chip_post_macro(0xfe) /* post fe */
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#ifdef SERIAL_CONSOLE
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TTYS0_TX_STRING($str_pre_main)
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#endif /* SERIAL_CONSOLE */
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/* memory is up. Let\'s do the rest in C -- much easier. */
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/* set new stack */
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movl $_estack, %esp
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#ifdef SMP
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movl $APIC_DEFAULT_BASE, %edi
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movl APIC_ID(%edi), %eax
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shrl $24, %eax
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movl $STACK_SIZE, %ebx
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mull %ebx
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subl %eax, %esp
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#endif
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/* push the boot_complete flag */
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pushl %ebp
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/* Save the stack location */
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movl %esp, %ebp
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/*
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* Now we are finished. Memory is up, data is copied and
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* bss is cleared. Now we call the main routine and
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* let it do the rest.
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*/
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intel_chip_post_macro(0xfe) /* post fe */
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#if defined(SERIAL_CONSOLE) && defined(DEBUG)
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TTYS0_TX_STRING($str_pre_main)
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#endif /* defined(SERIAL_CONSOLE) && defined(DEBUG) */
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/* memory is up. Let\'s do the rest in C -- much easier. */
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intel_chip_post_macro(0xfd) /* post fe */
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call EXT(intel_main)
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/* Resort the stack location */
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movl %ebp, %esp
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/* The boot_complete flag has already been pushed */
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call EXT(hardwaremain)
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/*NOTREACHED*/
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.Lhlt:
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intel_chip_post_macro(0xee) /* post fe */
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@ -109,3 +121,17 @@ str_after_ram: .string "Ram Initialize?\r\n"
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str_after_copy: .string "after copy?\r\n"
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str_pre_main: .string "before main\r\n"
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newline: .string "\r\n"
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.section ".reset_vector"
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.code16
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.globl EXT(reset_vector)
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EXT(reset_vector):
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#if _ROMBASE >= 0xffff0000
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jmp EXT(_start)
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#elif (_ROMBASE < 0x100000)
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ljmp $((_ROMBASE & 0xf0000)>>4),$EXT(_start_offset);
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#else
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#error _ROMBASE is an unsupported value
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#endif
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@ -9,6 +9,9 @@
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* _ROMBASE
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* : linuxbios text
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* : readonly text
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*
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* _ROMTOP : The top of the rom used where we
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* need to put the reset vector.
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*/
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/*
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* Bootstrap code for the STPC Consumer
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@ -18,6 +21,9 @@
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*
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*/
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_ROMTOP = (_ROMBASE >= 0xffff0000)? 0xfffffff0 : 0xffff0;
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_start_offset = _start & 0xffff;
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gdtptr_offset = gdtptr & 0xffff;
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/*
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* Written by Johan Rydberg, based on work by Daniel Kahlin.
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* Rewritten by Eric Biederman
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@ -28,13 +34,6 @@
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*/
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OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
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OUTPUT_ARCH(i386)
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/* oh, barf. This wont work if all you use is .o's. -- RGM */
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/* These are now set by the config tool
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_RAMBASE = 0x04000;
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_ROMBASE = 0x80000;
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*/
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/*
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* Entry point is not really nececary, since the mkrom(8)
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@ -49,18 +48,21 @@ SECTIONS
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* First we place the code and read only data (typically const declared).
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* This get placed in rom.
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*/
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.text _ROMBASE : {
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. = _ROMBASE;
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.text (.) : {
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_text = .;
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*(.text);
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*(.text.*)
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_etext = .;
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}
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.rodata (.) : {
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.rodata (.) : {
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_rodata = .;
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*(.rodata);
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*(.rodata)
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_erodata = .;
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}
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. = _RAMBASE;
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/*
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* After the code we place initialized data (typically initialized
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* global variables). This gets copied into ram by startup code.
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@ -68,17 +70,15 @@ SECTIONS
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* whereas __data_loadstart and __data_loadend shows where in rom to
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* copy from.
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*/
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.data (.): AT (_erodata) {
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.data (.): AT(_erodata) {
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_data = .;
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*(.data)
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*(.sdata)
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*(.sdata2)
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*(.got)
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_edata = .;
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}
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_ldata = LOADADDR(.data);
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_eldata = LOADADDR(.data) + SIZEOF(.data);
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_eldata = LOADADDR(.data) + SIZEOF(.data);
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/*
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* bss does not contain data, it is just a space that should be zero
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* initialized on startup. (typically uninitialized global variables)
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@ -96,21 +96,28 @@ SECTIONS
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.heap (.): {
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_heap = .;
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/* Reserve 256K for the heap */
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. = . + 0x40000;
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. = . + ( HEAP_SIZE );
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_eheap = .;
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}
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.stack (.) : {
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_stack = .;
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/* Resever 64k for the stack */
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. = . + 0x10000;
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/* Reserve 64k stack for each possible cpu */
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. = . + ((MAX_CPUS) * (STACK_SIZE));
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_estack = .;
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}
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_lreset = _eldata;
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. = _lreset;
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_deadspace = (_ROMTOP - _lreset);
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.reset (.) : AT (_lreset) {
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. = . + _deadspace;
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_reset_vector = .;
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*(.reset_vector)
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_ereset_vector = . ;
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. = . + (16 - (1 + (_ereset_vector - _reset_vector)));
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BYTE(0x00);
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}
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_elreset = _lreset + SIZEOF(.reset);
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/DISCARD/ : {
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*(*)
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}
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}
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/*
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* This provides the start and end address for the whole image
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*/
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_image = LOADADDR(.text);
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_eimage = LOADADDR(.data) + SIZEOF(.data);
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/* EOF */
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@ -1,25 +1,47 @@
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biosbase 0xf0000
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rambase 0x4000
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makedefine LINK = ld -T ldscript.ld -o $@ crt0.o linuxbios.a
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makedefine CPPFLAGS= -I$(TOP)/src/include -I$(TOP)/src/arch/$(ARCH)/include $(CPUFLAGS)
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makedefine CFLAGS= $(CPU_OPT) $(CPPFLAGS) -O2 -nostdinc -nostdlib -fno-builtin -Wall
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makedefine CC=cc
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option _ROMBASE=0xf0000
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option _RAMBASE=0x4000
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option ROM_IMAGE_SIZE=65536
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# By default we only have one cpu
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option MAX_CPUS=1
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# Reserve 256K for the heap
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option HEAP_SIZE=0x40000
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# Reserve 64K for each stack
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option STACK_SIZE=0x10000
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# By default on x86 we have a memory hole between 640K and 1MB
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option MEMORY_HOLE=1
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makedefine CC:=gcc
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makedefine CPP:= gcc -x assembler-with-cpp -DASSEMBLY -E
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makedefine LIBGCC_FILE_NAME := $(shell $(CC) -print-libgcc-file-name)
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makedefine GCC_INC_DIR := $(shell $(CC) -print-search-dirs | sed -ne "s/install: \(.*\)/\1include/gp")
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makedefine CPPFLAGS := -I$(TOP)/src/include -I$(TOP)/src/arch/$(ARCH)/include -I$(GCC_INC_DIR) $(CPUFLAGS)
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makedefine CFLAGS := $(CPU_OPT) $(CPPFLAGS) -O2 -nostdinc -nostdlib -fno-builtin -Wall
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makerule all : romimage ;
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makerule floppy : all ; mcopy -o romimage a:
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makerule romimage : linuxbios.rom vmlinux.bin.gz.block ; cat vmlinux.bin.gz.block linuxbios.rom > romimage
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makerule linuxbios.rom: linuxbios.strip mkrom ; ./mkrom -s 64 -f -o linuxbios.rom linuxbios.strip
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|
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makerule linuxbios.rom: linuxbios.strip ;
|
||||
addaction linuxbios.rom export size=`ls -l linuxbios.strip | (read p c u g size r ; echo $$size)` ; \
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addaction linuxbios.rom echo $$size ; \
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addaction linuxbios.rom dd if=linuxbios.strip of=linuxbios.rom bs=1 seek=`expr $(ROM_IMAGE_SIZE) - $$size`
|
||||
|
||||
makerule linuxbios.strip: linuxbios ; objcopy -O binary -R .note -R .comment -S linuxbios linuxbios.strip
|
||||
makerule linuxbios: linuxbios.a vmlinux.bin.gz ; @rm -f biosobject
|
||||
|
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makerule linuxbios.o : crt0.o linuxbios.a $(LIBGCC_FILE_NAME) ; $(CC) -nostdlib -r -o $@ crt0.o linuxbios.a $(LIBGCC_FILE_NAME)
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|
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makerule linuxbios: linuxbios.o ldscript.ld ; $(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld linuxbios.o
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addaction linuxbios nm -n linuxbios > linuxbios.map
|
||||
|
||||
makerule etags: $(SOURCES) ; etags $(SOURCES)
|
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makerule tags: $(SOURCES) ; gctags $(SOURCES)
|
||||
makerule documentation: $(SOURCES) ; doxygen LinuxBIOSDoc.config
|
||||
addaction linuxbios $(LINK)
|
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addaction linuxbios nm -n linuxbios > linuxbios.map
|
||||
|
||||
makerule linuxbios.a : $(OBJECTS) ; rm -f linuxbios.a
|
||||
addaction linuxbios.a ar cr linuxbios.a $(OBJECTS)
|
||||
|
||||
makerule crt0.s: crt0.S ; $(CC) $(CPPFLAGS) -I$(TOP)/src -E $< > crt0.s
|
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makerule crt0.s: crt0.S $(TOP)/src/cpu/p5/start32.inc ; $(CPP) $(CPPFLAGS) -I$(TOP)/src $< > crt0.s
|
||||
|
||||
makerule crt0.o : crt0.s; $(CC) $(CPU_OPT) -c crt0.s
|
||||
makerule mkrom: $(TOP)/mkrom/mkrom.c ; $(CC) -o mkrom $<
|
||||
|
|
|
|||
|
|
@ -261,6 +261,7 @@
|
|||
#define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001
|
||||
#define PCI_DEVICE_ID_AMD_SCSI 0x2020
|
||||
#define PCI_DEVICE_ID_AMD_FE_GATE_7006 0x7006
|
||||
#define PCI_DEVICE_ID_AMD_FE_GATE_700C 0x700C
|
||||
#define PCI_DEVICE_ID_AMD_COBRA_7400 0x7400
|
||||
#define PCI_DEVICE_ID_AMD_COBRA_7401 0x7401
|
||||
#define PCI_DEVICE_ID_AMD_COBRA_7403 0x7403
|
||||
|
|
@ -269,6 +270,11 @@
|
|||
#define PCI_DEVICE_ID_AMD_VIPER_7409 0x7409
|
||||
#define PCI_DEVICE_ID_AMD_VIPER_740B 0x740B
|
||||
#define PCI_DEVICE_ID_AMD_VIPER_740C 0x740C
|
||||
#define PCI_DEVICE_ID_AMD_VIPER_7410 0x7410
|
||||
#define PCI_DEVICE_ID_AMD_VIPER_7411 0x7411
|
||||
#define PCI_DEVICE_ID_AMD_VIPER_7412 0x7412
|
||||
#define PCI_DEVICE_ID_AMD_VIPER_7413 0x7413
|
||||
#define PCI_DEVICE_ID_AMD_VIPER_7414 0x7414
|
||||
|
||||
#define PCI_VENDOR_ID_TRIDENT 0x1023
|
||||
#define PCI_DEVICE_ID_TRIDENT_9320 0x9320
|
||||
|
|
@ -676,6 +682,8 @@
|
|||
#define PCI_DEVICE_ID_REALTEK_8129 0x8129
|
||||
#define PCI_DEVICE_ID_REALTEK_8139 0x8139
|
||||
|
||||
#define PCI_VENDOR_ID_TYAN 0x10f1
|
||||
|
||||
#define PCI_VENDOR_ID_TRUEVISION 0x10fa
|
||||
#define PCI_DEVICE_ID_TRUEVISION_T1000 0x000c
|
||||
|
||||
|
|
@ -1298,3 +1306,6 @@
|
|||
#define PCI_DEVICE_ID_ARK_STING 0xa091
|
||||
#define PCI_DEVICE_ID_ARK_STINGARK 0xa099
|
||||
#define PCI_DEVICE_ID_ARK_2000MT 0xa0a1
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,10 @@
|
|||
arch i386
|
||||
mainboardinit superio/acer/m1535/setup_serial.inc
|
||||
mainboardinit pc80/serial.inc
|
||||
northbridge acer/m1631
|
||||
southbridge acer/m1535
|
||||
superio acer/m1535
|
||||
mainboardinit cpu/p6/earlymtrr.inc
|
||||
|
||||
option ENABLE_FIXED_AND_VARIABLE_MTRRS
|
||||
option FINAL_MAINBOARD_FIXUP
|
||||
|
|
|
|||
|
|
@ -1,5 +1,9 @@
|
|||
arch i386
|
||||
mainboardinit superio/SMC/fdc37b907/setup_serial.inc
|
||||
mainboardinit pc80/serial.inc
|
||||
northbridge intel/440bx
|
||||
southbridge intel/piix4e
|
||||
mainboardinit cpu/p6/earlymtrr.inc
|
||||
|
||||
nsuperio SMC/fdc37b807
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,9 @@
|
|||
arch i386
|
||||
mainboardinit superio/ITE/it8671f/setup_serial.inc
|
||||
mainboardinit pc80/serial.inc
|
||||
northbridge intel/440bx
|
||||
southbridge intel/piix4e
|
||||
mainboardinit cpu/p6/earlymtrr.inc
|
||||
|
||||
superio ITE/it8671f
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,9 @@
|
|||
arch i386
|
||||
mainboardinit superio/SMC/fdc37c669/setup_serial.inc
|
||||
mainboardinit pc80/serial.inc
|
||||
northbridge intel/440bx
|
||||
southbridge intel/piix4e
|
||||
mainboardinit cpu/p6/earlymtrr.inc
|
||||
|
||||
superio SMC/fdc37c669
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,9 @@
|
|||
arch i386
|
||||
mainboardinit superio/NSC/pc87309/setup_serial.inc
|
||||
mainboardinit pc80/serial.inc
|
||||
northbridge intel/440gx
|
||||
southbridge intel/piix4e
|
||||
mainboardinit cpu/p6/earlymtrr.inc
|
||||
|
||||
superio NSC/pc87309
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,9 @@
|
|||
arch i386
|
||||
mainboardinit superio/SMC/fdc37n769/setup_serial.inc
|
||||
mainboardinit pc80/serial.inc
|
||||
northbridge intel/440bx
|
||||
southbridge intel/piix4e
|
||||
mainboardinit cpu/p6/earlymtrr.inc
|
||||
|
||||
superio SMC/fdc37n769
|
||||
option SMC_BASE=0x370
|
||||
|
|
|
|||
|
|
@ -1,8 +1,11 @@
|
|||
arch i386
|
||||
mainboardinit superio/winbond/w83977ef/setup_serial.inc
|
||||
mainboardinit pc80/serial.inc
|
||||
northbridge intel/440bx
|
||||
southbridge intel/piix4e
|
||||
superio winbond/w83977ef
|
||||
raminit northbridge/intel/440bx/raminit.inc
|
||||
mainboardinit cpu/p6/earlymtrr.inc
|
||||
|
||||
option INTEL_PPRO_MTRR
|
||||
option ENABLE_FIXED_AND_VARIABLE_MTRRS
|
||||
|
|
|
|||
|
|
@ -1,7 +1,10 @@
|
|||
arch i386
|
||||
mainboardinit superio/sis/950/setup_serial.inc
|
||||
mainboardinit pc80/serial.inc
|
||||
northsouthbridge sis/630
|
||||
# superio sis/950
|
||||
nsuperio sis/950 com1={1} floppy=1 lpt=1
|
||||
mainboardinit cpu/p6/earlymtrr.inc
|
||||
|
||||
option ENABLE_FIXED_AND_VARIABLE_MTRRS
|
||||
option FINAL_MAINBOARD_FIXUP
|
||||
|
|
|
|||
|
|
@ -1,7 +1,10 @@
|
|||
arch i386
|
||||
mainboardinit superio/sis/950/setup_serial.inc
|
||||
mainboardinit pc80/serial.inc
|
||||
northsouthbridge sis/630
|
||||
# superio sis/950
|
||||
nsuperio sis/950 com1={1} floppy=1 lpt=1
|
||||
mainboardinit cpu/p6/earlymtrr.inc
|
||||
|
||||
option ENABLE_FIXED_AND_VARIABLE_MTRRS
|
||||
option FINAL_MAINBOARD_FIXUP
|
||||
|
|
|
|||
|
|
@ -1,7 +1,10 @@
|
|||
arch i386
|
||||
mainboardinit superio/acer/m1535/setup_serial.inc
|
||||
mainboardinit pc80/serial.inc
|
||||
northbridge acer/m1631
|
||||
southbridge acer/m1535
|
||||
superio acer/m1535
|
||||
mainboardinit cpu/p6/earlymtrr.inc
|
||||
|
||||
option ENABLE_FIXED_AND_VARIABLE_MTRRS
|
||||
option FINAL_MAINBOARD_FIXUP
|
||||
|
|
|
|||
|
|
@ -1,7 +1,10 @@
|
|||
arch i386
|
||||
mainboardinit superio/sis/950/setup_serial.inc
|
||||
mainboardinit pc80/serial.inc
|
||||
northsouthbridge sis/730
|
||||
# superio sis/950
|
||||
nsuperio sis/950 com1={1} floppy=1 lpt=1
|
||||
mainboardinit cpu/p6/earlymtrr.inc
|
||||
|
||||
option ENABLE_FIXED_AND_VARIABLE_MTRRS
|
||||
option FINAL_MAINBOARD_FIXUP
|
||||
|
|
|
|||
|
|
@ -1,6 +1,10 @@
|
|||
arch i386
|
||||
mainboardinit superio/sis/950/setup_serial.inc
|
||||
mainboardinit pc80/serial.inc
|
||||
northsouthbridge sis/540
|
||||
# superio sis/950
|
||||
nsuperio sis/950 com1={1} floppy=1 lpt=1
|
||||
mainboardinit cpu/p6/earlymtrr.inc
|
||||
|
||||
option FINAL_MAINBOARD_FIXUP
|
||||
option HAVE_PIRQ_TABLE
|
||||
|
|
|
|||
|
|
@ -1,4 +1,6 @@
|
|||
arch i386
|
||||
northsouthbridge sis/550
|
||||
mainboardinit cpu/p6/earlymtrr.inc
|
||||
|
||||
option FINAL_MAINBOARD_FIXUP
|
||||
option HAVE_PIRQ_TABLE
|
||||
|
|
|
|||
8
src/mainboard/tyan/s1834/Config
Normal file
8
src/mainboard/tyan/s1834/Config
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
arch i386
|
||||
mainboardinit superio/winbond/w83977ef/setup_serial.inc
|
||||
mainboardinit pc80/serial.inc
|
||||
mainboardinit northbridge/via/vt8601/raminit.inc
|
||||
#mainboardinit ram/ramtest.inc
|
||||
#mainboardinit cpu/p6/earlymtrr.inc
|
||||
#mainboardinit mainboard/tyan/s1834/do_ramtest.inc
|
||||
mainboardinit cpu/p6/earlymtrr.inc
|
||||
5
src/mainboard/tyan/s1834/do_ramtest.inc
Normal file
5
src/mainboard/tyan/s1834/do_ramtest.inc
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
mov $0x00000000, %eax
|
||||
mov $0x0009ffff, %ebx
|
||||
mov $16, %ecx
|
||||
|
||||
CALLSP(ramtest)
|
||||
|
|
@ -1,7 +1,10 @@
|
|||
arch i386
|
||||
mainboardinit superio/via/vt82c686/setup_serial.inc
|
||||
mainboardinit pc80/serial.inc
|
||||
northbridge via/vt8601
|
||||
southbridge via/vt82c686
|
||||
superio via/vt82c686
|
||||
mainboardinit cpu/p6/earlymtrr.inc
|
||||
|
||||
option ENABLE_FIXED_AND_VARIABLE_MTRRS
|
||||
object mainboard.o
|
||||
|
|
|
|||
|
|
@ -1,7 +1,10 @@
|
|||
arch i386
|
||||
mainboardinit superio/via/vt82c686/setup_serial.inc
|
||||
mainboardinit pc80/serial.inc
|
||||
northbridge via/vt8601
|
||||
southbridge via/vt82c686
|
||||
superio via/vt82c686
|
||||
mainboardinit cpu/p6/earlymtrr.inc
|
||||
|
||||
option ENABLE_FIXED_AND_VARIABLE_MTRRS
|
||||
option SUPERIO_DEVFN=0x88
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
raminit northbridge/intel/440bx/raminit.inc
|
||||
raminit sdram/generic_sdram.inc
|
||||
raminit sdram/generic_sdram_enable.inc
|
||||
|
||||
object northbridge.o
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
raminit northbridge/intel/440gx/raminit.inc
|
||||
raminit sdram/generic_sdram.inc
|
||||
raminit sdram/generic_sdram_enable.inc
|
||||
|
||||
object northbridge.o
|
||||
|
|
|
|||
|
|
@ -1 +1,5 @@
|
|||
object keyboard.o
|
||||
object mc146818rtc.o
|
||||
object isa-dma.o
|
||||
object i8259.o
|
||||
|
||||
|
|
|
|||
|
|
@ -221,3 +221,4 @@ serial0:
|
|||
mov $TTYS0_LCR, %dx
|
||||
mov $0x03, %al
|
||||
out %al, %dx
|
||||
|
||||
|
|
|
|||
|
|
@ -2,4 +2,5 @@ object fill_inbuf.o
|
|||
object rom_fill_inbuf.o
|
||||
object docmil_fill_inbuf.o
|
||||
object tsunami_tigbus_rom_fill_inbuf.o
|
||||
object serial_fill_inbuf.o
|
||||
object tftp_fill_inbuf.o
|
||||
|
|
|
|||
32
src/rom/serial_fill_inbuf.c
Normal file
32
src/rom/serial_fill_inbuf.c
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
#ifdef USE_SERIAL_FILL_INBUF
|
||||
|
||||
#include <printk.h>
|
||||
#include <stdlib.h>
|
||||
#include <subr.h>
|
||||
#include <stddef.h>
|
||||
#include <rom/fill_inbuf.h>
|
||||
|
||||
#include <string.h>
|
||||
#include <serial_subr.h>
|
||||
|
||||
|
||||
static int firstfill = 1;
|
||||
static unsigned char *ram;
|
||||
|
||||
#define K64 (64*1024)
|
||||
|
||||
int fill_inbuf(void)
|
||||
{
|
||||
int rc;
|
||||
if (firstfill) {
|
||||
firstfill = 0;
|
||||
ram = malloc(K64);
|
||||
}
|
||||
inbuf = ram;
|
||||
insize = ttys0_rx_bytes(inbuf, K64);
|
||||
inptr = 1;
|
||||
return inbuf[0];
|
||||
}
|
||||
|
||||
|
||||
#endif /* USE_SERIAL_FILL_INBUF */
|
||||
|
|
@ -1,36 +1,13 @@
|
|||
jmp ram_initialize
|
||||
|
||||
/* Estimate that SLOW_DOWN_IO takes about 50&76us*/
|
||||
/* delay for 200us */
|
||||
|
||||
#define DO_DELAY \
|
||||
movl $4, %edi ; \
|
||||
1: SLOW_DOWN_IO ; \
|
||||
decl %edi ; \
|
||||
jnz 1b
|
||||
|
||||
|
||||
|
||||
ram_1: .string "Ram1\r\n"
|
||||
ram_2: .string "Ram2\r\n"
|
||||
ram_3: .string "Ram3\r\n"
|
||||
ram_4: .string "Ram4\r\n"
|
||||
ram_5: .string "Ram5\r\n"
|
||||
ram_6: .string "Ram6\r\n"
|
||||
ram_7: .string "Ram7\r\n"
|
||||
ram_8: .string "Ram8\r\n"
|
||||
ram_9: .string "Ram9\r\n"
|
||||
ram_10: .string "Ram10\r\n"
|
||||
ram_11: .string "Ram11\r\n"
|
||||
ram_12: .string "Ram12\r\n"
|
||||
ram_13: .string "Ram13\r\n"
|
||||
ram_14: .string "Ram14\r\n"
|
||||
ram_15: .string "Ram15\r\n"
|
||||
ram_16: .string "Ram16\r\n"
|
||||
ram_17: .string "Ram17\r\n"
|
||||
ram_18: .string "Ram18\r\n"
|
||||
ram_19: .string "Ram19\r\n"
|
||||
ram_20: .string "Ram20\r\n"
|
||||
|
||||
|
||||
no_memory_str: .string "No memory!\r\n"
|
||||
|
||||
no_memory: TTYS0_TX_STRING($no_memory_str)
|
||||
|
|
@ -53,65 +30,21 @@ ram_initialize:
|
|||
|
||||
TTYS0_TX_STRING($ram_3)
|
||||
|
||||
/* Now that everything is setup enable the SDRAM
|
||||
* Some chipsets do the work for us while on others
|
||||
* we need to do the work by hand.
|
||||
*/
|
||||
CALL_LABEL(enable_sdram)
|
||||
|
||||
/* now the fun begins.
|
||||
turn on the dram and wait a while (this from the intel book)
|
||||
turn power on and set the nop bit too
|
||||
*/
|
||||
TTYS0_TX_STRING($ram_4)
|
||||
/* SDRAMC */
|
||||
SET_RAM_COMMAND(RAM_COMMAND_NOP)
|
||||
|
||||
DO_DELAY
|
||||
|
||||
ASSERT_RAM_COMMAND() /* nop command */
|
||||
|
||||
/* Precharge all */
|
||||
SET_RAM_COMMAND(RAM_COMMAND_PRECHARGE)
|
||||
ASSERT_RAM_COMMAND()
|
||||
|
||||
/* wait until the all banks idle state... */
|
||||
|
||||
FIRST_NORMAL_REFERENCE()
|
||||
TTYS0_TX_STRING($ram_5)
|
||||
|
||||
/* Now we need 8 AUTO REFRESH / CBR cycles to be performed */
|
||||
|
||||
SET_RAM_COMMAND(RAM_COMMAND_CBR)
|
||||
ASSERT_RAM_COMMAND()
|
||||
ASSERT_RAM_COMMAND()
|
||||
ASSERT_RAM_COMMAND()
|
||||
ASSERT_RAM_COMMAND()
|
||||
ASSERT_RAM_COMMAND()
|
||||
ASSERT_RAM_COMMAND()
|
||||
ASSERT_RAM_COMMAND()
|
||||
ASSERT_RAM_COMMAND()
|
||||
|
||||
TTYS0_TX_STRING($ram_6)
|
||||
|
||||
/* mode register set */
|
||||
SET_RAM_MODE_REGISTER
|
||||
|
||||
/* MAx[14:0] lines,
|
||||
* MAx[2:0 ] 010 == burst mode of 4
|
||||
* MAx[3:3 ] 1 == interleave wrap type
|
||||
* MAx[4:4 ] == CAS# latency bit
|
||||
* MAx[6:5 ] == 01
|
||||
* MAx[12:7] == 0
|
||||
*/
|
||||
|
||||
TTYS0_TX_STRING($ram_7)
|
||||
|
||||
/* normal operation */
|
||||
SET_RAM_COMMAND(RAM_COMMAND_NONE)
|
||||
|
||||
FIRST_NORMAL_REFERENCE()
|
||||
TTYS0_TX_STRING($ram_8)
|
||||
|
||||
|
||||
/* Finally enable refresh */
|
||||
/* DRAMC */
|
||||
ENABLE_REFRESH()
|
||||
|
||||
SPECIAL_FINISHUP()
|
||||
|
||||
TTYS0_TX_STRING($ram_9)
|
||||
TTYS0_TX_STRING($ram_6)
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue