Vendorcode decides already in AMD_INIT_POST the exact location
of UMA memory. To meet alignment requirements, it will extend
uma_memory_size. We cannot calculate base from size and TOP_MEM1,
but need to calculate size from base and TOP_MEM1 instead.
Also allows selection of UmaMode==UMA_SPECIFIED to manually set
amount of memory reserved for framebuffer.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6ab4e00cbae38bbbc6f8633a3d77944a25a6ecdc
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e87564ffe7
Original-Change-Id: I0c375e5da0dfef6cef0c50272356cd32a87b1ff6
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19346
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/508779
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Vendorcode decides already in AMD_INIT_POST the exact location
of UMA memory. To meet alignment requirements, it will extend
uma_memory_size. We cannot calculate base from size and TOP_MEM1,
but need to calculate size from base and TOP_MEM1 instead.
Also allows selection of UmaMode==UMA_SPECIFIED to manually set
amount of memory reserved for framebuffer.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie72f645e841d758ad4a275c39111c3a785ddd883
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 61be3603f4
Original-Change-Id: I2514c70a331c7fbf0056f22bf64f19c9374754c0
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19328
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/508778
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
A left-over from 5e3cb72a71 (nb/x4x: Do not enable IGD when not
supported). Should fix coverity issue 1375009. Remove a redundant
line that uses the variable `gfxsize` out of its scope and move the
variable declaration. Make sure the variable is always initialized,
drop unneeded error-handling for `get_option()` and sanitize the
read value instead.
BUG=none
BRANCH=none
TEST=none
Change-Id: If91dd643c754fd049952065dba56bab731b7f449
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: cfd433b96d
Original-Change-Id: Iee2beda30d8c74df0f412622c3ff3357819e386b
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/19680
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/506219
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
`cardF[n]` should indicate whether the DIMM in channel n is of
raw card type F. However, `cardF[1]` was initialised with the
value meant for `cardF[0]`. This patch results in the correct
initialisation of `cardF`.
Tested on a Lenovo T400 containing two DIMMs: one of raw card
type F and the other of raw card type B. Before the patch, the
system would not boot. After the patch, the system boots with all
of the memory functional.
BUG=none
BRANCH=none
TEST=none
Change-Id: If1d8dd58d2a9953a2d6318efcfecd8ce6d8a5425
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 12e6562289
Original-Change-Id: I7409df0b8c67d7efbdadae39dc718c8df7a92552
Original-Signed-off-by: Tristan Corrick <tristancorrick86@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19652
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/506210
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This results in raminit_receive_enable_calibration.c producing
no errors or warnings with checkpatch.
The issues fixed are:
ERROR: that open brace { should be on the previous line
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
Tested by compiling after making the changes.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4aec07bcaba5721297f432194310163d75925d7d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 267d086a08
Original-Change-Id: I8d2f4f1fe2f17aa44c0a7090c178eee418defe78
Original-Signed-off-by: Tristan Corrick <tristancorrick86@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19651
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/506209
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib2a34ccafd64aefcd9795e162a15a2fab3e15696
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 30670121c3
Original-Change-Id: I5322d731a0dc655f2da14b87fa6cbc1e54b5abd5
Original-Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/18522
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/506207
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Currently only one board uses this northbridge in coreboot but some
patches are pending to add more.
BUG=none
BRANCH=none
TEST=none
Change-Id: I05077218d6e434d9c52a86cf53003959afca435b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 512a2d1c4f
Original-Change-Id: If035e442d1a23674667f46a07b44c4f2b81be48c
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19650
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/506177
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I58e973e472aa54b20b373c3a795516b1485f87d8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1dcb2ac199
Original-Change-Id: I2308b069b8f2c601254169bcb6a34442c537a311
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19649
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/506176
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I81abfe539a145d88017047d36c36cf6c54b65ae0
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c5fba2c17c
Original-Change-Id: I15550b1cc1a7ccfecba68a46ab2acaee820575b9
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19648
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/506175
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Is only present on the P45 subtype of chipset.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iac30ec9f12a559730bf3e786301d7f5882caff52
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 293445ae1f
Original-Change-Id: I6b138db6654c83c40b5ca4b65d6ccd51ad4277fa
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18516
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/506168
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
According to "Intel 4 Series Chipset Family datasheet" in the
description about GGC and DEVEN, CAPID0 bit46 is said to reflect the
presence of an internal graphic device. This would allow the P43 and
P45 chipset variants to work.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic71a7c81d494e91f4aee97fe489a4df29b99843f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5e3cb72a71
Original-Change-Id: Icdaa2862f82000de6d51278098365c63b7719f7f
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18515
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/501157
The NGI writes to legacy VGA registers which should not happen when
VGA cycles are assigned to a different device.
TESTED on ga-g41m-es2l
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibd9669589a05f5ec776c3f9bc81de65266ced83e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2e7efe65a2
Original-Change-Id: I0a03e35c0d7f2532edd6cc5e62d1cf07dab57f60
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19607
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/501156
This disables VGA cycles on IGD when an external VGA device is
found. This allows PCI or PCIe devices to be the 'main' VGA device if
found, while the IGD is still available.
TESTED on ga-g41m-es2l: SeaBIOS shows payload on external GPU while
linux (4.10) can use both as a framebuffer simultaneously without any
extra configuration.
BUG=none
BRANCH=none
TEST=none
Change-Id: I31fa03ca83a31ec741bd0dff3c4cffe57021581d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c80748c2d0
Original-Change-Id: I74890918feb0f1ff6b971c4aaa96f1f7b75266ac
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18504
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/501155
Computes TSEG size dynamically.
Changes the size of legacy hole to match other Intel northbirdges.
Refactor this a little by needing one less variable.
BUG=none
BRANCH=none
TEST=none
Change-Id: I71eccc97aee616652c992d87753c54a60fd1c023
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4c4f56a6ba
Original-Change-Id: I0e6898c06a2bc1016eeaa3f002ff6c39657018ae
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18511
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/501154
This code ought not to run if ME is disabled. It also prohibits
writing to some GMCH regs like GGC bit1.
Intel 4 Series Chipset Family datasheet refers to this as
"ME stolen Memory lock" without actually describing this
functionality.
BUG=none
BRANCH=none
TEST=none
Change-Id: I2515e965aafbac95e78eef9a42ce10c302c892d7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ddc8828697
Original-Change-Id: Iaa8646e535e13c44c010ccd434a5af954cf7dfbc
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18513
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/501147
Use register name instead of hex value.
No functional change.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3ed947b8d353083053e801d555239f2805bfe717
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5c31af8e1a
Original-Change-Id: Iacfe609f6454e6d58c9733f425377464238ce4a9
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19544
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/498309
The checkreset() function checks if raminit previously
succeeded (pmcon2 bit7 == 0). If this is not the case it will issue a
hot reset (writing 0x6 to 0xcf9). On the next attempt to boot the
system BOOT_PATH_RESET path will be taken. This boot path can only
successfully initialize memory if the system was reset from a state
where raminit succeeded, which is not the case here.
This can be fixed by issuing a cold reset instead of a hot reset.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4b9d826e63c89a67190c8acfe9ce8e459f77623e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8565c03caf
Original-Change-Id: Idbcf034c3777a64cc3fb92dc603d10470a6c8cb6
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19506
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/497394
Add some known good values for some thinkpads displays.
Known good means that at this pwm frequency the display is evenly lit
on all duty cycles, the display makes minimal to no noise at lower
duty cycles and the display does not flicker. This values differs from
vendor (which uses an obviously wrong display clock (190MHz instead
of 320MHz) resulting in frequency more than 60% off the intended
value.
TESTED on Thinkpad X200 with edid ascii string in list and removed
from list to see if notice message is shown.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6df100df0f80ce479ace6ee2c1d59114c17f1a7a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 20cb85fa98
Original-Change-Id: Id7bc0d453fac31e806852206ba2c895720b2c843
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19500
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/496055
This allows to use EDID data outside of NGI path without needing to
fetch it twice.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iae2da8ce54bcdbe4836a900bb0ef43b333366153
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 53485d2eab
Original-Change-Id: I6a540b1d036a9f38b44fd004309601630861f6e7
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19503
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/496053
Claim memory-mapped regions in the legacy area.
Claim an MMIO resource for the A000 and B000 segments, and reserved
resource for C000 through F000 segments.
These changes allow code and information to be retained in the event
unused regions get wiped.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit d612d4fe69881609d42053496409c452e1014947)
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic5f61a63499db3b882f06ec4c8642519196d1a88
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6a7ebd4e08
Original-Change-Id: I9c47c919bbfd0edccf752e052f32d1e47c1a1324
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19156
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/494048
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Set up IGD OpRegion in northbridge and fill in GNVS' aslb.
At this point GNVS already has been set up by SSDT injection.
Required for future VBT patches that will:
* Use ACPI memory instead of CBMEM
* Use common implementation to locate VBT
* Fill in platform specific values
BUG=none
BRANCH=none
TEST=none
Change-Id: I4dee11445385e7c6189593d8a09558e5cd8b7bac
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 281ccca373
Original-Change-Id: I97c3402ac055991350732e55b0dda042b426c080
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19310
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/493984
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Set up IGD OpRegion in northbridge and fill in GNVS' aslb.
At this point GNVS already has been set up by SSDT injection.
Required for future VBT patches that will:
* Use ACPI memory instead of CBMEM
* Use common implementation to locate VBT
* Fill in platform specific values
BUG=none
BRANCH=none
TEST=none
Change-Id: I355d6a04d31cb42a6113e32429a82eea0f924d0b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2be2840a1d
Original-Change-Id: I76b31fe5fd19b50b82f57748558fb04408e0fd23
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19309
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/493983
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Set up IGD OpRegion in northbridge and fill in GNVS' aslb.
At this point GNVS already has been set up by SSDT injection.
Required for future VBT patches that will:
* Use ACPI memory instead of CBMEM
* Use common implementation to locate VBT
* Fill in platform specific values
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib359f8a42946da6a293b456ca087b899d53cf9cc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d0eb6cd8bd
Original-Change-Id: Ie5d93117ee8bd8d15085aedbfa7358dfcf5f0045
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19307
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/493982
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
This needs some extra headers in amdk8/raminit.c that were otherwise
provided by that file.
BUG=none
BRANCH=none
TEST=none
Change-Id: I93fc04d84b412f5db1c80766f28d1f31d8d8fe6a
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 3eff00ec76
Original-Change-Id: I80450e5eb32eb502b3d777c56790db90491fc995
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19360
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/490681
Add a check for vboot when locating the binaryPI image.
There is currently an ordering problem using cbmem to locate the
image when vboot is present. Vboot inserts its locator into the
search process so that memory can be checked before flash is queried.
For the earliest calls using the wrapper, DRAM has not been set up
and cbmem not initialized in romstage. This change prevents an
endless loop when vboot searches cbmem.
This change has another side effect. When vboot is in effect, the
change forces the RO binaryPI to be used even when on either of the
RW paths. There is currently no ability to relocate the XIP image
for use in a RW region.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 6efe9217c38cf93fd9b38e52cf3ec90fee3d0474)
BUG=none
BRANCH=none
TEST=none
Change-Id: If30b23954f97cc4565ff81b55ee3a9e4145be379
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ca3815b4c5
Original-Change-Id: I0c14bd729f8a67bca37cbdbd3a5e266c99c86d54
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18438
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/490076
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
The devicetree data structures have been available in more than just
ramstage and romstage. In order to provide clearer and consistent
semantics two new macros are provided:
1. DEVTREE_EARLY which is true when !ENV_RAMSTAGE
2. DEVTREE_CONST as a replacment for ROMSTAGE_CONST
The ROMSTAGE_CONST attribute is used in the source code to mark
the devicetree data structures as const in early stages even though
it's not just romstage. Therefore, rename the attribute to
DEVTREE_CONST as that's the actual usage. The only place where the
usage was not devicetree related is console_loglevel, but the same
name was used for consistency. Any stage that is not ramstage has
the const C attribute applied when DEVTREE_CONST is used.
BUG=none
BRANCH=none
TEST=none
Change-Id: If0409e8e9d6a203254a9f9b749de5cab70dfc842
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e4d7abc0d4
Original-Change-Id: Ibd51c2628dc8f68e0896974f7e4e7c8588d333ed
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19333
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/488047
For raminit to succeed on a hot reset the following things are
prevented from running:
* Clearing self refresh
* Setting memory frequency
* programming sdram dll timings
* programming rcomp
TESTED on Intel d510mo.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3c561f2bcffeb7e76159c529049c7aaeb7143a13
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 00fd3ff507
Original-Change-Id: I8f7e5c2958df29a96cdf856ade2f4f33707ad362
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19337
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/486761
The function decode_spd uses undeclared variables and an incorrectly
initialized array.
BUG=none
BRANCH=none
TEST=none
Change-Id: I896b374368ecc4e217297402ac98d93a059bf4c3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 097d753980
Original-Change-Id: Ib45a8b2946c04c270e29524675b1f09d491d282b
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19336
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/486741
Hide some (partial) lines behind DEBUG_RAM_SETUP and shorten
some messages. This saves some KiB to make CBMEM console more
usable in romstage.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia059932c6328ea4dab09714dd2a9eca2b00808b9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0624f92118
Original-Change-Id: I62a84ca662ee778b7c1deb71247f3b01a37858fa
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/19318
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/482963
Adds the necessary plumbing for acpi_device_path() to find the LPC
bridge on the AMD Family10h/15h northbridges and SB700 southbridge.
This is necessary for TPM support since the acpi path to the LPC bridge
doesn't match the built-in default in tpm.c
This is a port of GIT hash d8a2c1fb by Tobias Diedrich.
BUG=https://ticket.coreboot.org/issues/102
Change-Id: I119547820e94fd1cd2baf814ef2595b43362efe0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0f3a18ad28
Original-Change-Id: I1c514e335e194b2864599e5419cfaee830b94e38
Original-Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Reviewed-on: https://review.coreboot.org/19282
Original-Tested-by: build bot (Jenkins)
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/480297
The x4x northbridge can be paired with either an ICH7 (in the case of
g41) or an ICH10 (all other cases: g45, q45, p45, ...). Only ICH10
sometimes occurs with a descriptor, gbe and an ME region.
ICH7 is always descriptorless so it makes no sense to fix CBFS to
accommodate for those other objects.
BUG=none
BRANCH=none
TEST=none
Change-Id: I150ac6c49ed853522802c5c948c61699fe123925
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4bc9c28811
Original-Change-Id: I4a01dfdbce1807e44932a3ac812110382332abd8
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19181
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/480289
Includes the DRAM controller device that knows which where the division
between addresses routed to the main memory and to the PCI bus is.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9246a4b6ddeec914efe99c2df7b13eeb5166577d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 38d1eb4403
Original-Change-Id: Id4cfeb8ff32de37723eee68a61c576e657dad30b
Original-Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Original-Reviewed-on: https://review.coreboot.org/18896
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/480280
This is the actual PCI Id of the internal graphics.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4b703e94434fc2a6fb13a17dff29f030dc4933c4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 43156f6625
Original-Change-Id: I2a25ed35a5b01de6da905619fa9fce96738d1c0e
Original-Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Original-Reviewed-on: https://review.coreboot.org/18895
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/480279
Without them the BS_DEV_RESOURCES stage won't traverse the bridge and
the graphics controller would be left without resources assigned.
Even worse, the resources would stay based in offset 0 which confuses
the MTRR setting code and causes a good chunk of the DRAM to be set
to type write combining.
With the patch applied, the resources are set:
Show resources in subtree (Root Device)...After assigning values.
...
PCI: 00:01.0 child on link 0 PCI: 01:00.0
+ PCI: 00:01.0 resource base ffff size 0 align 0 gran 0 limit ffff flags 60080100 index 0
+ PCI: 00:01.0 resource base f8000000 size 4000000 align 26 gran 0 limit fbffffff flags 60081200 index 1
+ PCI: 00:01.0 resource base fc000000 size 1010000 align 24 gran 0 limit fd00ffff flags 60080200 index 2
PCI: 01:00.0
- PCI: 01:00.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 1200 index 10
- PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 14
- PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30
+ PCI: 01:00.0 resource base f8000000 size 4000000 align 26 gran 26 limit fbffffff flags 60001200 index 10
+ PCI: 01:00.0 resource base fc000000 size 1000000 align 24 gran 24 limit fcffffff flags 60000200 index 14
+ PCI: 01:00.0 resource base fd000000 size 10000 align 16 gran 16 limit fd00ffff flags 60002200 index 30
And the caching mode is set properly:
MTRR: Physical address space:
-0x0000000000000000 - 0x0000000004000000 size 0x04000000 type 1
-0x0000000004000000 - 0x000000000e000000 size 0x0a000000 type 6
-0x000000000e000000 - 0x0000000100000000 size 0xf2000000 type 0
+0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
+0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
+0x00000000000c0000 - 0x000000000e000000 size 0x0df40000 type 6
+0x000000000e000000 - 0x00000000f8000000 size 0xea000000 type 0
+0x00000000f8000000 - 0x00000000fc000000 size 0x04000000 type 1
+0x00000000fc000000 - 0x0000000100000000 size 0x04000000 type 0
The problem was also spot and discussed here:
http://coreboot.coreboot.narkive.com/E9eGauzH/via-c7-on-bcom-winnet-p680-l1-l2-cache-very-slow
BUG=none
BRANCH=none
TEST=none
Change-Id: I5368a607d44f0f0afae0a3d1ecc424f0fa8cb9bd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2523dd031c
Original-Change-Id: Idb4979b206838dd6455b2a16de14dc74f83af921
Original-Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Original-Reviewed-on: https://review.coreboot.org/18894
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/480278
Otherwise, it locks up quickly. Not sure which ones are actually needed
and why, couldn't bisect it into removing even a single one.
The factory BIOS on a Neoware G170 does 200 0xed reads between setting
the registers too.
BUG=none
BRANCH=none
TEST=none
Change-Id: I11e149bad93bc05eb6e7ef8373ad4ae834d02633
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b31a066e0d
Original-Change-Id: I6aa38768d84dd42c9c720c917a99e6b4b1e03427
Original-Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Original-Reviewed-on: https://review.coreboot.org/18893
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/480110
Vendor BIOS leaves UPMC1 untouched (on 945gc the default is 0x0203).
Not running PCIEx16 init which is valid for 945gm seems to fix all
issues and instabilities related to the PEG port.
According to lspci the link width is at the desired x16.
It is unknown if devices requesting a lower width work automatically
or need more configuration.
What happens is that IGD gets disabled by the disable function in
gma.c when an external GPU is found unless
CONFIG_ONBOARD_VGA_IS_PRIMARY is set.
Setting IGD as secondary makes Linux (4.10) hang, so this behavior is
a requirement for now.
TESTED on P5GC-MX with a discrete GPU and both
CONFIG_ONBOARD_VGA_IS_PRIMARY set and unset.
BUG=none
BRANCH=none
TEST=none
Change-Id: I305d73ec4472f7df1618d5da29853ffcfb048e30
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2f6b52e3a0
Original-Change-Id: I6da8aa7714073f4b34df5ae3c1eb4c19e27ddc97
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18549
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/480104
This is needed if one wants to use the header more than once.
BUG=none
BRANCH=none
TEST=none
Change-Id: If43ac3dafbb8e6b9052d6af9206d586d5a466ce1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f170e71630
Original-Change-Id: I375d08465b6c64cd91e7563e3917764507d779ba
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19029
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/474135
All boards select INTEL_EDID, move it to nb folder.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie41e0d5dc6a50e9b2ba170cf1ad6c25b74a47f2e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 46cf5c29b3
Original-Change-Id: I35f075a87f2d841856b208f9440cf41af6a3c8e6
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19086
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/472711
Move odt stretch into own function.
Apply workaround on SandyBridge C-stepping CPU only.
Apply odt stretch on all other CPU types.
Don't depend on empty DIMM detection, as in case one slot
is empty ref_card_offset is zero.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie348a49ed33b841503f0e54b24969f7faf02b546
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 19c3dad0ad
Original-Change-Id: I4320f14e0522ec997b1f9f3b12ba2c2070ee8e9e
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/17616
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/472709
quick_ram_check doesn't change contents of memory.
Run it in S3 resume, too.
BUG=none
BRANCH=none
TEST=none
Change-Id: I903fd25adfa117b0b466a7c191ae2bf54d7af867
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 77db3e153b
Original-Change-Id: Icaf3650fadbb3bb87d8c780a9e79737c3cf7eb06
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/17615
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/472708
