erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

UPSTREAM: nb/intel/x4x: Define and use default MMCONF_BASE_ADDRESS

Browse source 
Currently only one board uses this northbridge in coreboot but some
patches are pending to add more.

BUG=none
BRANCH=none
TEST=none

Change-Id: I05077218d6e434d9c52a86cf53003959afca435b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 512a2d1c4f
Original-Change-Id: If035e442d1a23674667f46a07b44c4f2b81be48c
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19650
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/506177
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Arthur Heymans 2017-05-10 13:12:37 +02:00 • committed by chrome-bot
commit 4d30fc943a
2 changed files with 4 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

4
src/mainboard/gigabyte/ga-g41m-es2l/Kconfig
View file

@ -35,10 +35,6 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_CMOS_DEFAULT
select HAVE_ACPI_RESUME
config MMCONF_BASE_ADDRESS
hex
default 0xe0000000
config MAINBOARD_DIR
string
default "gigabyte/ga-g41m-es2l"

4
src/northbridge/intel/x4x/Kconfig
View file

@ -38,4 +38,8 @@ config VGA_BIOS_ID
string
default "8086,2e32"
config MMCONF_BASE_ADDRESS
hex
default 0xe0000000
endif