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UPSTREAM: nb/intel/x4x: Add support for second PEG slot

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Is only present on the P45 subtype of chipset.

BUG=none
BRANCH=none
TEST=none

Change-Id: Iac30ec9f12a559730bf3e786301d7f5882caff52
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 293445ae1f
Original-Change-Id: I6b138db6654c83c40b5ca4b65d6ccd51ad4277fa
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18516
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/506168
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Arthur Heymans 2017-02-27 21:45:07 +01:00 • committed by chrome-bot
commit 596d63e7aa
1 changed files with 9 additions and 2 deletions
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11
src/northbridge/intel/x4x/northbridge.c
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@ -196,8 +196,12 @@ static void x4x_init(void *const chip_info)
struct device *const d0f0 = dev_find_slot(0, 0);
/* Hide internal functions based on devicetree info. */
for (dev = 3; dev > 0; --dev) {
for (dev = 6; dev > 0; --dev) {
switch (dev) {
case 6: /* PEG1: only on P45 */
fn = 0;
bit_base = 13;
break;
case 3: /* ME */
fn = 3;
bit_base = 6;
@ -206,10 +210,13 @@ static void x4x_init(void *const chip_info)
fn = 1;
bit_base = 3;
break;
case 1: /* PEG */
case 1: /* PEG0 */
fn = 0;
bit_base = 1;
break;
case 4: /* Nothing to do */
case 5:
continue;
}
for (; fn >= 0; --fn) {
const struct device *const d =