Always read the rmu.bin file from the read-only section of the SPI
flash. Without this change vboot attempts to read this file from the
A or B section of the flash.
TEST=Build and run on Galileo Gen2
Change-Id: I236241e92774d323475f2baf4f6d527142f9ae67
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 70bb05715a
Original-Change-Id: Ied8eaa2cd37645bf401aa957936943946bfd6182
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18803
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/455831
Fix the following error detected by checkpatch.pl:
ERROR: code indent should use tabs where possible
TEST=Build and run on Galileo Gen2
Change-Id: If82533a86037d743c997cd6a042b4eca9bcbe856
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 006d73d2e2
Original-Change-Id: Ief4b96073b3df30e45bf5d802ca3b190e7f431a7
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18753
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/455828
Since asking CSE to read FPF status turned out to be slow in some
cases, cache and save returned value on first boot only. Value is
read from flash on consequent boots.
BUG=b:35586975
BRANCH=reef
TEST=boot twice, make sure cached FPF status is loaded from
flash the second time.
Change-Id: Ida11aa2c7dc47dc791162af12bbe1a7e59de1ff1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c5f3685f44
Original-Change-Id: I6e56a35407c9097616ccb05a557fded7b639c88a
Original-Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18774
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/455827
Fix build error with FSP 1.1. Pass the S3 wake status to
fsp_silicon_init.
TEST=Build and run on Galileo Gen2
Change-Id: Icd837562ee4ace32219296013f0fd818ba74ab07
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1e24bf3f71
Original-Change-Id: I78150f737321db5b1b4d63b411fa6432ac30d080
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18805
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/455824
Return NULL for top_of_memory when the register has not been set.
TEST=Build and run on Galileo Gen2
Change-Id: I86684044fc282eaa8deda2b5dbd8ab6cae095d72
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6edb314050
Original-Change-Id: If79cac68c2a64aa9bf3be72d3cfc4c73fceef12b
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18802
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/455822
Extract SMBIOS memory information from FSP SMBIOS_MEM_INFO_HOB
and save it in CBMEM.
BUG=chrome-os-partner:61729
BRANCH=none
TEST=Build and boot KBLRVP to verify the type 17 DIMM info coming in
SMBIOS Table from Kernel command "dmidecode".
Change-Id: I6550af3135c9a5626292b81c6c93856ec7243818
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b7fa7fbbd7
Original-Change-Id: I593d4ccb0d4866e99913a73c49b2f000b51827d1
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18275
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/455037
Add the files to support verstage for vboot.
TEST=Build and run on Galileo Gen2
Change-Id: Ic1312c0be3b987e85f07bc5f8fe49705166d7d9e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b8f5323107
Original-Change-Id: Icf87075012c08cf581c17d579e0763888c707265
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18040
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/454573
Fix the following warning detected by checkpatch.pl:
WARNING: line over 80 characters
TEST=Build for reef
Change-Id: Ib6f457d2f7bf367ddf538c61f3c2d8efc6cab532
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 07441b5ae6
Original-Change-Id: I4fbe95037ca4b52e64ba37e5c739af4a03f64feb
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18728
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/454569
Fix the following errors and warnings detected by checkpatch.pl:
ERROR: switch and case should be at the same indent
ERROR: do not use assignment in if condition
WARNING: Statements terminations use 1 semicolon
WARNING: unnecessary whitespace before a quoted newline
WARNING: else is not generally useful after a break or return
TEST=Build for reef
Change-Id: Icd638905143cbe0ea2ae692ac137fae76e9daf06
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a444753596
Original-Change-Id: I5486936dbf19b066c76179d929660affa1da5f16
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18727
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/454568
Fix the following error and warning detected by checkpatch.pl:
ERROR: inline keyword should sit between storage class and type
WARNING: storage class should be at the beginning of the declaration
TEST=Build for reef
Change-Id: Ie77611f00d3eda395c8f3f3a1ce8e130949bfd9e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2d154e8213
Original-Change-Id: I2ed418cc3b4a989eb1101013944169429bf147c2
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18726
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/454567
Fix the following errors and warning detected by checkpatch.pl:
ERROR: space required before the open parenthesis '('
ERROR: space prohibited before that close parenthesis ')'
ERROR: return is not a function, parentheses are not required
WARNING: space prohibited between function name and open parenthesis '('
TEST=Build for reef
Change-Id: Ia137d5c6bb4416931dfe87fce69137de5888996f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d8fb362ea0
Original-Change-Id: I31f854adf3269ba6f77c4044fb3748bb1957841c
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18725
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/454566
Fix the following warning detected by checkpatch.pl:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
TEST=Build for reef
Change-Id: I61a84be89ab8a95e1cf6bc27054e9c50b44613a9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0096d07274
Original-Change-Id: Ifc45ce90d466d087cd20af72ddfc8486d2f1492c
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18724
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/454565
Fix the following warnings detected by checkpatch.pl:
WARNING: braces {} are not necessary for any arm of this statement
WARNING: braces {} are not necessary for single statement blocks
TEST=Build for reef
Change-Id: If5e634a92e3f2f1a2a9a609898eedf95de6f878b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4430f9f75d
Original-Change-Id: Ifab09c023faa7da215945f1aedd391f4b2a1a04c
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18723
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/454564
Fix the following error and warnings detected by checkpatch.pl:
ERROR: code indent should use tabs where possible
WARNING: please, no spaces at the start of a line
WARNING: please, no space before tabs
TEST=Build for reef
Change-Id: Ie2f65ba5f25f405ba238223035147f7a427e70a8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1d20fe77cb
Original-Change-Id: Id7a758463b95274c5e8bbdd67da0955f1ae78aac
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18721
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/454563
Fix the following errors detected by checkpatch.pl:
ERROR: spaces required around that '==' (ctx:VxO)
ERROR: space required before that '-' (ctx:OxV)
ERROR: spaces required around that '=' (ctx:VxW)
ERROR: spaces required around that '=' (ctx:WxV)
ERROR: spaces required around that '=' (ctx:VxV)
ERROR: need consistent spacing around '+' (ctx:VxW)
ERROR: space prohibited before that '++' (ctx:WxB)
ERROR: space prohibited before that ',' (ctx:WxW)
ERROR: space required after that ',' (ctx:VxV)
TEST=Build for reef
Change-Id: I9dd232ad0df0ed6d344e2e8109fdbaa9b835f487
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 320b7ca44b
Original-Change-Id: I37265a69fcb14fbf7c182ef29d823f70a5748ad8
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18720
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/454562
Fix the following errors detected by checkpatch.pl:
ERROR: "foo * bar" should be "foo *bar"
ERROR: "(foo*)" should be "(foo *)"
TEST=Build for reef
Change-Id: I7fa59c65c0b536f9ee4a9f6371b253dc771bbce1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 68571c144e
Original-Change-Id: I4a762d8fa762057a06e601dfed10538adc5d8bc8
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18719
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/454561
Fix the following error detected by checkpatch.pl:
ERROR: open brace '{' following function declarations go on the next line
TEST=Build for reef
Change-Id: I15fbc181c58350a6a426d225e6057e9638e52602
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bab8be229a
Original-Change-Id: Icb92dc49c6e7b8dfea60bc0395f3db7316c4e34c
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18722
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/454560
Fix the following error detected by checkpatch.pl:
ERROR: return is not a function, parentheses are not required
TEST=Build and run on Galileo Gen2
Change-Id: Idf0dc83cec44a59369333d6bb3f44099d533278a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8fbd953ffb
Original-Change-Id: Idf7723d4fd48124a26bbb626afc310820f859f66
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18757
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/454541
Fix the following warning detected by checkpatach.pl:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
TEST=Build and run on Galileo Gen2
Change-Id: I4a4dc3bab94a5f6c1fd8ee691233a1e2d30ebc76
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 20727813bb
Original-Change-Id: Ic266c077eb115e0c7d934c15bcc4cc9b9e530a39
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18756
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/454540
Fix the following errors detected by checkpatch.pl:
ERROR: spaces required around that '=' (ctx:VxV)
ERROR: spaces required around that ':' (ctx:VxW)
ERROR: space required after that ',' (ctx:VxV)
ERROR: space required before the open parenthesis '('
ERROR: switch and case should be at the same indent
ERROR: "foo ** bar" should be "foo **bar"
TEST=Build and run on Galileo Gen2
Change-Id: I7dad3594007ffdb5d45a548731c694d9729bf2be
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 68ab0b5d1f
Original-Change-Id: I52ba2a3c1e0fffad7145eecd878aba8dc450ac0b
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18755
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/454539
Fix the following error detected by checkpatch.pl:
ERROR: code indent should use tabs where possible
TEST=Build and run on Galileo Gen2
Change-Id: If26414313050f4e9a045cf64e0dd9b007b34d610
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 42e605be19
Original-Change-Id: I61c4f01216cb6c788cf6da988c414bbb9648d502
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18754
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/454538
BUG=b:35647967
TEST=boot from bob
Change-Id: I055ad5f59285cee3110d1e7cb1a53a60144712e4
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/452285
Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
In strncpy() function of dimm_info_fill(), the minimum possible size
of Module Part Number of DIMM is passed as argument.
BUG=chrome-os-partner:61729
BRANCH=none
TEST=Build and boot KBLRVP to verify the type 17 DIMM info coming in
SMBIOS Table from Kernel command "dmidecode".
Change-Id: Id26d55a11f8c4bcbdedc6c34d7b48198e2501f4f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6497cd9744
Original-Change-Id: Icc7667149eae9705b91e271628af1b443eb8556e
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18617
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/453361
CDClk selection was wrong in some corner cases (e.g. ULX SKUs) and,
for Broadwell, never took the devicetree config into account.
Rewrite the selection with the following in mind:
o cpu_is_ult() might return `true` for ULX SKUs, too,
o ULX and Broadwell-ULT SKUs can be `overclocked` with additional
cooling, so leave that as devicetree option.
For Haswell, the following frequency selections are valid:
o ULX: 337.5MHz by default, 450MHz optional
o ULT: 450MHz only (maybe 337.5MHz too, documentation varies,
it wasn't selectable before either)
o others: 540MHz by default, 450MHz optional
For Broadwell:
o ULX: 450MHz by default, 337.5MHz / 540MHz optional
o ULT: 540MHz by default, 337.5MHz / 450MHz / 675MHz optional
o others: 667MHz by default, 337.5MHz / 450MHz / 540MHz optional
Side effects: A too high setting in the devicetree results in the
highest possible frequency now, Haswell non-ULT/ULX defaults to 540MHz
instead of 450MHz.
BUG=none
BRANCH=none
TEST=none
Change-Id: I2539a6b66b677217a2c5e44c4fe2fc7b8b5624bc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e392f414cd
Original-Change-Id: Iec12752f2a47bf4a5ae6077c75790eae9378c1b2
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/17768
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/453358
Reserve the whole TZRAM area because it will be marked as secure-only
by BL31 and can not be accessed by the non-secure kernel.
CQ-DEPEND=CL:452659
BUG=chrome-os-partner:57361
BRANCH=firmware-gru-8785.B
TEST=the reserve memory is resized
Change-Id: I39c4cb530f41a7b0f7f3064125072dd85b62276f
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/418102
Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit ea9fe064a9b1e1ce81fca74f829a0fb6e78ce426)
Reviewed-on: https://chromium-review.googlesource.com/452640
Tested-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Julius Werner <jwerner@chromium.org>
eMMC Controller is taking over 100ms to resume during runtime which
results in I/O latency issues on the Skylake systems like Cave and Caroline.
This patch adds _DSM method for eMMC comtroller for specifying the
device readiness durations. Function index 9 returns package of five
integers to set D3 cold delay to zero and ACPI constant Ones for the
elements where overriding the default values is not desired.
BUG=b:35774937
BRANCH=none
TEST=update caroline coreboot and test i/o latency is under 100ms
Change-Id: I7ebb13c7f72279c9c1727f68e0ad96949715bf9a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d448a5e98b
Original-Change-Id: Iacc8aa8560897da8770fe559ca8cd17aaf6ebeba
Original-Signed-off-by: Sowmya V <v.sowmya@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18532
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/452896
This implements dynamic generation of sdcard GpioInt in SSDT.
GpioInt in SSDT generation is based on the card detect GPIO if
it is provided by the mainboard in devicetree.
This implements GNVS variable to store the address of sdcard cd pin.
GNVS used to store rxstate of the sdcard cd pin to get card presence.
Add _PS0/_PS3 methods to power gate the sd card controller in
S0ix and runtime PM.
CQ-DEPEND=CL:448173
BUG=chrome-os-partner:63070
TEST=Suspend and resume using 'echo freeze > /sys/power/state'.
System should enter S0ix and resume with no issue.
Change-Id: I13a4250606be8adb7a180b4ec3f58e89f197101b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6dd7b402d5
Original-Change-Id: Id2c42fc66062f0431385607cff1a83563eaeef87
Original-Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18496
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/452893
Add two GPIO macros:
1. PAD_CFG_GPI_APIC_EDGE allows a pin to be route to the
APIC with input assuming the events are edge triggered.
2. PAD_CFG_GPI_ACPI_SCI_LEVEL to route the general purpose
input to SCI assuming the events are level triggered.
BUG=none
BRANCH=none
TEST=none
Change-Id: I38f8bb09537eaf41c89d584db767bda484181416
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 75d8d8da47
Original-Change-Id: I944a9abac66b7780b2336148ae8c7fa3a8410f3f
Original-Signed-off-by: Rahul Kumar Gupta <rahul.kumarxx.gupta@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18533
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/452472
Add SKL/KBL PCH-H GPIO settings referring from SKL PCH-H
specifications to support sklrvp11.
Split the gpio_defs.h into headers gpio_pch_h_defs.h and
gpio_soc_defs.h for PCH-H specific and SOC specific GPIO
defs respectively.
BUG=none
BRANCH=none
TEST=none
Change-Id: I598225ee81d49b70965374bb888d3e3ad3c600bb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6a740539d1
Original-Change-Id: I5eaf8d809a1244a56038cbfc29502910eb90f9f2
Original-Signed-off-by: Li Cheng Sooi <li.cheng.sooi@intel.com>
Original-Signed-off-by: Rahul Kumar Gupta <rahul.kumarxx.gupta@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18027
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/452471
Apollolake platform comes with FPF (field-programmable-fuses). FPF can
be blown only once, typically at the end of the manufacturing process.
This patch adds code that sends a request to CSE to figure out if FPFs
have already been blown.
BUG=none
BRANCH=none
TEST=none
Change-Id: I45d74923d7b4dc8adb8bfa812965694abd75d5ee
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b1aded2f0c
Original-Change-Id: I9e768a8b95a3cb48adf66e1f17803c720908802d
Original-Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18604
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452370
Add common driver that can send/receive HECI messages. This driver is
inspired by Linux kernel mei driver and somewhat based on Skylake's.
Currently it has been only tested on Apollolake.
BUG=b:35586975
BRANCH=reef
TEST=tested on Apollolake to send single messages and receive both
fragmented and non-fragmented versions.
Change-Id: Ia22e402e626e4da9dd75c934cbf0e142d1ec990e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 04a72c4019
Original-Change-Id: Ie3772700270f4f333292b80d59f79555851780f7
Original-Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18547
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452368
If Deep Sx is enabled the event log will get entries added on every
power sequence transition indicating that the suspend well has failed.
When a board is using Deep Sx by design this is intended behavior and
just fills the logs with extraneous events.
To make this work the device init state has to be executed first so it
actually enables the Deep Sx policies in the SOC since this code does
not have any hooks back into the devicetree to read the intended setting
from there.
BUG=b:36042662
BRANCH=none
TEST=Perform suspend/resume on Eve device with Deep S3 enabled, and
then check the event log to be sure that it does not contain the
"SUS Power Fail" event.
Change-Id: I8455c68e305a3c098d6a823c1586a8db77c88666
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ac2cbd0ffb
Original-Change-Id: I3c8242baa63685232025e1dfef5595ec0ec6d14a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18664
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/452360
Add a function to read the current state of Deep S5 configuration
and indicate if it is enabled (for AC and/or DC) or disabled.
This is similar to the existing function that checks Deep S3
enable state.
BUG=b:36042662
BRANCH=none
TEST=tested with subsequent commits to check Deep S5 state at boot
and filter event log messages if it is enabled.
Change-Id: I5aaa847908d0ab3468310e69414a08875777a78f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cb76d50f0d
Original-Change-Id: I4b60fb99a99952cb3ca6be29f257bb5894ff5a52
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18663
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/452359
Add options to the skylake chip config that will allow tuning the
various settings that can affect acoustics with the CPU and its VRs.
These settings are applied inside FSP, and they can adjust the slew
slew rate when changing voltages or disable fast C-state ramping on
the various CPU VR rails.
BUG=b:35581264
BRANCH=none
TEST=these are currently unused, but I verified that enabling the
options can affect the acoustics of a system at runtime.
Change-Id: I9445eb29c9f3089f68f1445fce8fb50464bf10cf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b2aac85030
Original-Change-Id: I6a8ec0b8d3bd38b330cb4836bfa5bbbfc87dc3fb
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18662
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452358
Fix the errors detected by checkpatch and update the copyright dates.
TEST=Build and run on Galileo Gen2
Change-Id: I17cf98c093c6b89bf6216c0c566c5b7309483579
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 94b971a909
Original-Change-Id: Idad062eaeca20519394c2cd24d803c546d8e0ae0
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18591
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/451421
Fix the following issues:
* A raw read is described by a single read segment, don't assert.
* Support reads longer than the FIFO size.
* Support writes longer than the FIFO size.
* Use the 400 KHz clock by default.
* Remove the error displays since vboot device polling generates
errors.
TEST=Build and run on Galileo Gen2
Change-Id: I0abfb0dd6247a089c7b0c5548dde6f509141f05a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 16568c7535
Original-Change-Id: I421ebb23989aa283b5182dcae4f8099c9ec16eee
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18029
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/451360
Move all common MSRs as per IA SDM into a common location
to avoid duplication.
BUG=none
BRANCH=none
TEST=none
Change-Id: Idfb8d874d83e38c112a07bea24909b6493717cfd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c2fd0a2114
Original-Change-Id: I06d609e722f4285c39ae4fd4ca6e1c562dd6f901
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18509
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/451261
Support for voltage margining is dependent on the platform.
Enabling voltage margining puts additional constraints for
the SLP_S0# to be asserted and hence moving to S0ix state.
If the platform PMIC/VR supports PCH voltage reduction,
voltage marigining can be enabled.
Use the UPD provided by FSP to enable/disable voltage margining.
BUG=none
BRANCH=none
TEST=none
Change-Id: I5d75e043dadf8adc6ed1e7a7800dd525ff76116b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0da186c3ff
Original-Change-Id: Iea214e9d7d6126e8367426485c6446ced63caa66
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18469
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/450241
Fix a typo that was introduce in commit 696ebc2d (Broadwell/Sata:
Add support for setting IOBP registers for Ports 2 and 3.) [1].
Setting one of the SATA port 3 IOBP setting was using the value from
the port 2 register.
On the purism/librem13 (on which SATA port 3 is tested), this change
doesn't seem to affect anything, as that typo wasn't exhibiting any
visible problems anyways.
[1] https://review.coreboot.org/18408
BUG=none
BRANCH=none
TEST=none
Change-Id: I872b03d4d4d28ae77d1cfe315da6a336c555817b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 601aa313a6
Original-Change-Id: I3948def5c0588791009c4b24cbc061552d9d1d48
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/18514
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/449825
Save SMBIOS memory information from FSP MEM_INFO_DATA_HOB in CBMEM.
Add function dimm_info_fill() which populates SMBIOS memory
information from FSP MEM_INFO_DATA_HOB data.
BUG=chrome-os-partner:61729
BRANCH=none
TEST=Build and boot KBLRVP to verify the type 17 DIMM info coming in
SMBIOS table from Kernel command "dmidecode".
Change-Id: I489ff93622c18183115b9d7a0cb62a22a96bdc3e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e13b77564f
Original-Change-Id: I0fd7c9887076d3fdd320fcbdcc873cb1965b950c
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18418
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/449821
The differential signal of DQS need keep low
level before gate training. RPULL will connect
4Kn from PADP to VSS and a 4Kn from PADN to
VDDQ to ensure it.But if it have PHY side ODT
connect at this time,it will change the DQS
signal level.So it need disable PHY side ODT
when do gate training.
BRANCH=None
BUG=None
TEST=boot from bob
Change-Id: I33cf743c3793a2765a21e5121ce7351410b9e19d
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/448278
Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Derek Basehore <dbasehore@chromium.org>
