GCC generates correct code for __builtin_bswapXX() on all architectures,
including ArmV4. It seems that whatever bug caused this to not work back
in commit 879ea7fce8 ("endian: Replace explicit byte swapping with
compiler builtin") has been fixed now. We can eliminate the swabXX()
functions and simplify the code.
All instances that had been calling these functions directly should have
been using real endianness conversions anyway.
Change-Id: I19713fd009aa5c0e01c4a42e0cf012364d6bed60
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90438
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
In preparation for the upcoming DSI dual channel support, pass dsi_regs
and mipi_tx_regs to DSI functions that need to access these registers.
BUG=b:424782827
TEST=util/abuild/abuild -x -t GOOGLE_SAPPHIRE -a
BRANCH=none
Change-Id: Ia0c9051148e38a7703119f800d417f2f8b52f78a
Signed-off-by: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90446
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add dsi_register_v3.h to define dsi_regs struct for mt8196, and add
dsi_reg.h to define mipi_tx_regs struct. Unlike other SoCs, mt8196
has dsi1 and mipi_tx1 registers in order to support DSI dual channel.
BUG=b:424782827
TEST=util/abuild/abuild -x -t GOOGLE_SAPPHIRE -a
BRANCH=none
Change-Id: I2b541c89a007f380de482bffa86aca60c351b526
Signed-off-by: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90451
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Move dsi0 variable definition to dsi_register_v*.h to be closer to the
register struct definition. This also allows us to define dsi1 for
mt8196 at the same place as dsi0 in a future patch. The dsi1 variable
cannot be defined in dsi_common.h because not all MediaTek SoCs using
the header have the DSI1_BASE register.
BUG=b:424782827
TEST=util/abuild/abuild -x -t GOOGLE_SAPPHIRE -a
BRANCH=none
Change-Id: I643f8d0317d0fb8bd8ea7bf8870ec99051c35c1b
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90452
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The soc/dsi.h header contains SoC-specific dsi and mipi_tx register
definitions, which are not needed for SoCs not supporting MIPI DSI
panels (such as mt8195). To decouple the generic display.c (used for
both eDP and MIPI panels) from those register definitions, move the
mtk_dsi_init() declaration and MIPI_DSI_* enums to display_dsi.h.
This allows us to remove the unused soc/dsi.h for mt8195.
BUG=b:424782827
TEST=util/abuild/abuild -x -t GOOGLE_ASURADA -a
TEST=emerge-skywalker coreboot
BRANCH=none
Change-Id: I56e458ec8077ed48929637b9b5c70f08653cc73f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90449
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In an upcoming change, a dsi_regs/mipi_tx_regs argument will be added to
functions declared in dsi_common.h. Currently those structs are all
defined in soc/dsi.h. However, dsi_common.h cannot include soc/dsi.h
because soc/dsi.h already includes dsi_common.h. To solve the circular
dependency issue, move the dsi_regs/mipi_tx_regs definitions to a new
file soc/dsi_reg.h.
As mt8183/mt8186/mt8188/mt8189/mt8192 all share compatible mipi_tx_regs
definitions, create a common mipi_tx_reg_v1.h and include it in these
SoCs' soc/mipi_tx_reg.h. The mt8173 remains its own struct definition.
Also, rename MIPITX_BASE to MIPITX0_BASE in soc/addressmap.h, to have
consistent naming across all SoCs. Note that MIPITX1_BASE will be added
for mt8196 in a future patch.
BUG=b:424782827
TEST=emerge-skywalker coreboot
BRANCH=none
Change-Id: I0e2159fde5bfc358691a4b3bdebc2657f0a598a8
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90445
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The address of mipi_tx1 should be MIPI_TX1_BASE instead of
MIPI_TX0_BASE. This doesn't cause any issue in practice because mipi_tx1
is unused.
Also rename lvds_tx1/lvds_tx2 to lvds_tx0/lvds_tx1 for consistency with
the MIPI_TX0_BASE/MIPI_TX1_BASE naming.
BUG=none
TEST=none
BRANCH=none
Change-Id: I040b0a2a447333141cf6f4a012fa5d2aefd936c7
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90444
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Kabylake SoC, Intel common, and ChromeEC.
TEST=build/boot google/eve, verify CFR option functionality.
Change-Id: Id878bbd06b7eb06f12c063486fd475c742a9a13b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tidy up before adding a new CFR entry in a subsequent patch.
Change-Id: I14dc011622acad43b6a21a00d97a958ea6d3152f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90320
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Sandy/Ivybridge, C216 SB, and ChromeEC.
TEST=build/boot google/link, verify CFR option functionality.
Change-Id: I08cccf136f20018aee925372b5c181bf4b55e0cd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90319
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
IPU cameras on popp-based devices are currently not properly supported
under Windows, which causes the camera status LED to be permanently on
when using Windows. To work around this, add a CFR option to disable
the IPU camera(s) on a given board.
TEST=build/boot google/poppy (nocturne), verify camera status LED is
off when CFR option disable and Windows booted.
Change-Id: I664ecac47211350b861504c3075e524f045dbf40
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Kabylake SoC, Intel common, and ChromeEC.
TEST=build/boot google/poppy (nocturne), verify CFR option
functionality.
Change-Id: Ib63c2a105a715a540a93b6163ff7e6f86deab5d0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Skylake SoC, Intel common, and ChromeEC.
TEST=build/boot google/glados (chell), verify CFR option
functionality.
Change-Id: Ie124d69e979c7d0ca8dd119046412cb637eb04da
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from ChromeEC.
TEST=build/boot google/skyrim (frostflow), verify CFR option
functionality.
Change-Id: Ife5b20725794cdecc47f632e10421b86ceac68a5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90315
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from ChromeEC.
TEST=build/boot google/guybrush (dewatt), verify CFR option
functionality.
Change-Id: I16e80e2ba1e51617956043137cd8fee1400b57f2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90314
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from ChromeEC.
TEST=build/boot google/zork (morphius), verify CFR option functionality
Change-Id: I21f6d01ab425fb698872735bca3514ae366bcdda
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from ChromeEC.
TEST=build/boot google/kahlee (liara), verify CFR option functionality
Change-Id: I19f059f1e0c0e7c71e5e84560fe72f271d33412c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Cometlake SoC and Intel common.
TEST=build/boot google/sarien, verify CFR option functionality.
Change-Id: Id7b023cecba36ac4a5c65eb5ece05361e8881980
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Meteorlake SoC, Intel common, and ChromeEC.
TEST=build/boot google/rex (karis), verify CFR option functionality.
Change-Id: Ic115272f69c2b37263d7ca0f921e6d9eceaaa8c3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Alderlake SoC, Intel common, and ChromeEC.
Change-Id: I99505f3f8b24c2f89329a3164963e874f5861374
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
The i2c auto-detection cannot distinguish between two touchpads using
the same i2c bus and address, so drop the 'detect' flag amd implement
a user-selectable CFR option instead, defaulting to both enabled.
This will allow either touchpad to work properly under Linux, and
give the user the ability to only enable the touchpad actually present
should they wish to run Windows.
Change-Id: Iaf1406c2d10bbf10b9aea30ae1cd2b2281bfcc5d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
The i2c auto-detection fails to find a touchscreen on Drawcia, so
create a user-selectable CFR option instead, with the default being
all enabled. This allows Linux to probe and detect the correct
device, and Windows users to select the appropriate selection.
Change-Id: I2e4a760b7d6c9b1546418630f75538adccdcf8e1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Jasperlake SoC, Intel common, and ChromeEC.
TEST=build/boot google/dedede (maglia), verify CFR option
functionality.
Change-Id: I36b567a32232cb0f561c9f428157e421319d8dab
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Alderlake SoC, Intel common, and ChromeEC.
TEST=build/boot google/brya (yaviks), verify CFR option functionality.
Change-Id: I4b450fbc3e376dcb256a2c6b8ca7fb2267fa5df3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Tigerlake SoC, Intel common, and ChromeEC.
TEST=build/boot google/volteer (drobit), verify CFR option
functionality.
Change-Id: Ic6848825aefa8e0627240fc04b2a6b7a33188de6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Cometlake SoC and Intel common.
TEST=build/boot google/drallion, verify CFR option functionality.
Change-Id: I9cff10b4782f6066e79cca8d39cb7cbc053d88ea
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90345
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tidy up before adding a new CFR entry in a subsequent patch.
Change-Id: Ifbb52e9930998187dcd310a50449b312f56e20e3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Cometlake SoC, Intel common, and ChromeEC.
TEST=build/boot google/hatch (akemi), verify CFR option
functionality.
Change-Id: I29158a2d1fe6956799156fbe066ad4e97c110226
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Geminilake SoC, Intel common, and ChromeEC.
TEST=build/boot google/octopus (ampton), verify CFR option
functionality.
Change-Id: I5ed3e038684c852c71bd812d6a4b8d05290d5361
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Apollolake SoC, Intel common, and ChromeEC.
TEST=build/boot google/reef (electro), verify CFR option
functionality.
Change-Id: I8d9fdcaccc2d5cf35dcea6042f0a73d4bfd7ce69
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90341
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allow users to enable/disable automatic fan control via CFR options
menu.
TEST=build/boot puff (wyvern) w/edk2 payload, verify automatic fan
control toggle functional.
Change-Id: I188e4393776b986809cbb1e51accaa88864b667f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90311
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Allow users to enable/disable automatic fan control via CFR options
menu.
TEST=build/boot fizz w/edk2 payload, verify automatic fan control
toggle functional.
Change-Id: I40e72b21f34e943b0f4bd6a206d004d89ec9692a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90310
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
CFR options are added for the following options:
- legacy_8254_timer
- s0ix_enable
- vtd
TEST=build/boot google/reef with CFR support
Change-Id: Ia58bf53f93742417c2aac683c96f7c8f382a35c0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Increase size of SMMSTORE FMAP region to 512KB to ensure a large
enough area is allocated to UEFI variable storage which allows for
variables (such as the UEFI revocation database) to be updated
via fwupd. Previously, such updates would fail with an error such as:
"efivar: No space left on device".
Change-Id: Ic959d5242879a991da93b33d3bf73beeb1448723
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Increase size of SMMSTORE FMAP region to 512KB to ensure a large
enough area is allocated to UEFI variable storage which allows for
variables (such as the UEFI revocation database) to be updated
via fwupd. Previously, such updates would fail with an error such as:
"efivar: No space left on device".
Change-Id: I1ef876de4ccb3a0ed2ff0a96b66c6b02bf274a3e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Increase size of SMMSTORE FMAP region to 512KB to ensure a large
enough area is allocated to UEFI variable storage which allows for
variables (such as the UEFI revocation database) to be updated
via fwupd. Previously, such updates would fail with an error such as:
"efivar: No space left on device".
Change-Id: Ia7566b31991b6891b4c194ad9b494da2e5ea8e01
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90290
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Increase size of SMMSTORE FMAP region to 512KB to ensure a large
enough area is allocated to UEFI variable storage which allows for
variables (such as the UEFI revocation database) to be updated
via fwupd. Previously, such updates would fail with an error such as:
"efivar: No space left on device".
Change-Id: I4073f7d1aed589544f072c2a64cada2cdddbe8bf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The previous default size of 256KB provided for only 64KB of actual
space for EFI variables, and after accounting for fragmentation, did
not provide enough free space for applying updates, such as for the
UEFI revocation database (DBX). Increasing it to 512KB allows for
192KB space for variables, and allows the UEFI DBX to be updated
properly via fwupd.
TEST=build/boot google/drobit, verify UEFI DBX able to be successfully
updated via fwupd.
Change-Id: I8d6a2051f3ad50117d41cec2bbbe3aaafa7e65c2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90287
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
sysinfo contains both CBMEM_ID_MEMINFO and CBMEM_ID_MEM_CHIP.
This new function allows to easily retrieve the amount of memory the
system has based on the mentioned CBMEM entries structures.
BUG=b:450374306
TEST=Checked on Google/Brya/Omnigul (x86) - MEMINFO
TEST=Checked on Google/Rauru/Navi (ARM64) - MEM_CHIP
Change-Id: Iaf69c54dfb3d2eaffbccacee8bee3be425b78a3f
Signed-off-by: Jakub Czapiga <czapiga@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90430
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For FVM, the function should be enable and set VR Fast Vmode ICC Limit
in BIOS.
According to VRTT test result by PWM IC vendor tuning.
VCCCORE VR Fast Vmode ICC Limit can set as 74A.
VCCGT VR Fast Vmode ICC Limit can set as 38A.
VCCSA VR Fast Vmode ICC Limit can set as 38A.
BUG=b:464422702
TEST=Build and check the system could boot to OS
Change-Id: Ia9dffbfde8d57044392b742d68c62398d6f3dfa3
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Correct "APCI" to "ACPI" in the UI help text.
Change-Id: I56343c82b2ddc73e565501f723538fbe96877cd6
Signed-off-by: Integral <integral@member.fsf.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90431
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We've accumulated a number of endianness-handling and related macros
that are duplicated between coreboot and libpayload. This patch reduces
duplication by merging them into a commonlib header. This has the added
side-benefit of bringing the coreboot implementation of beXXenc/dec()
functions to libpayload, which lead to better code generation by
avoiding https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92716.
Keep the htobell()-style functions in libpayload only since they're not
needed in coreboot and not preferred. Keep the cpu_to_beXX()-style
functions in coreboot only -- maybe we should deprecate those
eventually.
This patch is explicitly copying and relicensing some of the code I
originally added as GPLv2 in commit e8e92d60c4 ("endian.h: Add
be32dec/be32enc family of functions") to BSD-3.
Change-Id: I5eb83d44a98b3aa59bba65b8e22df668874d2668
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90308
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
coreboot produces SMBIOS tables with version 3.0.0. The UEFI payload
may overwrite this value based on PCDs and cause a mismatch of the
SMBIOS tables version produced by coreboot and version visible to OS.
To ensure proper parsing of SMBIOS tables in OS, set the same version
of SMBIOS for UEFI payload using the PCDs.
TEST=Run dmidecode on Gigabyte MZ33-AR1 and see that the tool reports
SMBIOS 3.0.0 present.
Change-Id: Ie3cdcca65dbcdddc74cb352ef5c4d3e83bdc87f5
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
TF-A feature additions have increased BL31 memory requirements. Expand
BL31 reservation from 600KB to 800KB and adjust the TA region start
address to prevent overlap. The TA region change requires FDT memory
reservation updates, which are handled in Depthcharge.This update
ensures proper memory alignment for secure firmware execution.
TEST=Created image.serial.bin and verified successful boot on X1P42100.
Basic device boot functionality with the updated memory reservation has
been validated.
Change-Id: Ia0145c9e8d5925de4a7fee3399efc76059944c10
Signed-off-by: Kirubakaran E <kirue@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
AMD systems have a TOM2WB bit in SYS_CFG MSR to forcefully cover the
address space between 4GB-TOM2 as WB. Any WB MTRR that falls into that
range may be skipped from programming. It can save a lot of MTRRs when
calculating the MTRR solution. It is especially needed when using a
temporary MTRR to cover the flash as WP, as the MTRR space gets more
fragmented.
Add checks for SYS_CFG TOM2WB in the MTRR driver and skip the WB MTRR
ranges when possible.
TEST=Successfully enable temporary MTRR range for flash on Gigabyte
MZ33-AR1.
Change-Id: Ie9af9b54a1037c843d8f019506af761a8d8769d0
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89199
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
clock enablement
Add register address and clock value definitions required to enable
the display clock. The register details are part of HRD-X1P42100-S1
document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
TEST=Generated image.serial.bin and verified boot on X1P42100.
Validated only basic device boot functionality, as clock enablement API
and its invocation sequence from display driver are not yet implemented.
Change-Id: Id23dd12c9c1ee4968546c8b928f9360163446a9d
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
