The CPUCP (CPU Control Processor) binary is currently stored
uncompressed in the RO region. To save space in the RO section
while maintaining fast boot performance in normal mode, split the
CPUCP CBFS entry into two distinct files:
1. cpucp_rw: Stored in FW_MAIN_A and FW_MAIN_B with no compression
for performance.
2. cpucp_ro: Stored in the COREBOOT (RO) region with LZMA
compression to save flash space.
Update the loading logic in cpucp_load_reset.c to select the
appropriate binary based on the current vboot mode (Normal vs.
Recovery).
BUG=None
TEST=Verified that CPUCP loads from 'cpucp_rw' during normal boot
and 'cpucp_ro' when vboot recovery is triggered.
Normal Mode:
```
[INFO ] CBFS: Found 'fallback/cpucp_rw' @0xc8640 size 0x79244
in mcache @0x8669d628
```
Recovery Mode:
```
[INFO ] CBFS: Found 'fallback/cpucp_ro' @0xc8640 size 0x79244
in mcache @0x8669d628
```
Change-Id: Iec5294beec4377b13f8b7354d86055d5907c6556
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This pulls in the following change from the submodule:
- add binaries for V2000A
Change-Id: I606f7926bcdef2a02ed1f492f37a0d7aefa27714
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91856
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
aarch64-elf nm doesn't support '--no-weak'. Replace the 'nm --no-weak'
call with 'grep' with "[TDRCB]" pattern to collect the non-weak
symbols.
Change-Id: I19195034b31f39086946b7e5ee15317d6f5dd880
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
On Faegan the FSP supports RAS. Allow the user to configure
RAS features and pass them to the FSP using UPDs.
Change-Id: Ia7091d216a446d56632e64f9bba0e2a166410139
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91819
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Create the dirkson variant of the dirks project by
copying the files to a new directory named for the variant.
BUG=b:494049087
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_DIRKSON
Change-Id: I7e1257ebe8292e00a282eb75535466dcb2b459eb
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
The TBMC ACPI device is used by Windows ChromeEC drivers to determine
tablet mode and to enable motion sensors (accelerometer, gyroscope).
Since it's not needed/used by ChromeOS, restrict its inclusion to
non-ChromeOS builds.
TEST=build/boot Win11/Linux on eldrid, verify tablet mode and rotation
work properly, keyboard/touchpad disabled in tablet mode.
Change-Id: I65832388649daceb498c91e6405d2b8343ca2aeb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
The TBMC ACPI device is used by Windows ChromeEC drivers to determine
tablet mode and to enable motion sensors (accelerometer, gyroscope).
Since it's not needed/used by ChromeOS, restrict its inclusion to
non-ChromeOS builds.
TEST=build/boot Win11/Linux on magolor, verify tablet mode and rotation
work properly, keyboard/touchpad disabled in tablet mode.
Change-Id: I6853465ba77be1f95cbe5795b318df02ecc1da39
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91798
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The TBMC ACPI device is used by Windows ChromeEC drivers to determine
tablet mode and to enable motion sensors (accelerometer, gyroscope).
Since it's not needed/used by ChromeOS, restrict its inclusion to
non-ChromeOS builds.
TEST=build/boot Win11/Linux on taeko, verify tablet mode and rotation
work properly, keyboard/touchpad disabled in tablet mode.
Change-Id: Ie26cd77c8a58034dbce05a1ab308b9dcc122484c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91797
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TMBC support has been backported to the EC firmware for CYAN
and KEFKA, so add SCI support for the MODE_CHANGE host event.
TEST=build/boot Win11, Linux on CYAN, verify tablet mode switching
functional via Intel VBTN driver.
Change-Id: Id3474e07bad1b6371644821dfe39a8105e4dd0f8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Set SYSTEM_TYPE_CONVERTIBLE for Volteer-based Spin/Flip devices
so SMBIOS reports a convertible enclosure type. This enables
EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS on non-ChromeOS builds
and allows use of the vendor tablet mode ACPI (VBTN).
Set the default SYSTEM_TYPE for non-convertibles to LAPTOP as
is done for most newer ChromeOS boards.
Change-Id: I02337464953fdb654e99019af4d2f142e1910e97
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Set SYSTEM_TYPE_CONVERTIBLE for Reef-based Spin/Flip devices
so SMBIOS reports a convertible enclosure type. This enables
EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS on non-ChromeOS builds
and allows use of the vendor tablet mode ACPI (VBTN).
Change-Id: Iff5c8379ff318a5616fee0133fef6f0ad9b93003
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Set SYSTEM_TYPE_CONVERTIBLE for Octopus-based Spin/Flip devices
so SMBIOS reports a convertible enclosure type. This enables
EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS on non-ChromeOS builds
and allows use of the vendor tablet mode ACPI (VBTN).
Change-Id: I298fb413480f6392990d00dc375db4d1e4176d9d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Set SYSTEM_TYPE_CONVERTIBLE for Hatch-based Spin/Flip devices
so SMBIOS reports a convertible enclosure type. This enables
EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS on non-ChromeOS builds
and allows use of the vendor tablet mode ACPI (VBTN).
Change-Id: I8b72efb176087dda29b1c32b7ceef4c4544ef4d7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91748
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set SYSTEM_TYPE_CONVERTIBLE for the CAROLINE variant so SMBIOS
reports a convertible enclosure type. This allows non-ChromeOS
builds to enable EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS and use
the vendor tablet mode ACPI.
Change-Id: I67429b34a197cb4f1e3938040b0b1853462796c3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Set SYSTEM_TYPE_CONVERTIBLE for Dedede-based Spin/Flip devices
so SMBIOS reports a convertible enclosure type. This enables
EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS on non-ChromeOS builds
and allows use of the vendor tablet mode ACPI (VBTN).
Adjust the system type check in mainboard_init() to account for
both laptops and convertibles.
Change-Id: I8cce636eb7e8ae6dfe16d6cd5004f463b5a7dd2d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91745
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set SYSTEM_TYPE_CONVERTIBLE for Brya 360/flip variants so SMBIOS
reports a convertible enclosure type. This allows non-ChromeOS
builds to enable EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS and use
the vendor tablet mode ACPI (VBTN).
Change-Id: I84bfd1df72d24b717f2b89906fd8dd2bef38d2b5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Introduce EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS to control inclusion of
Intel VBTN and AMD VGBI ACPI devices used for tablet/convertible mode.
Default is y for non-ChromeOS builds when the board selects
SYSTEM_TYPE_CONVERTIBLE or SYSTEM_TYPE_DETACHABLE.
Add vbtn.asl (Intel INT33D6/INT33D3) and vgbi.asl (AMD AMD33D6/AMD33D3).
In ec.asl, gate VBTN/VGBI notify and these includes on the new config.
Boards that are convertibles or detachables will enable the vendor
tablet controls by selecting the appropriate SMBIOS enclosure type in
subsequent changes.
Change-Id: I208c1f1856a9223af5109464ecf316e76de3a976
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91742
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
In scenarios where the system is booting with a critical or low battery,
lowering the initial CPU frequency helps reduce the instantaneous power
draw, ensuring the battery can sustain the boot process while fast
charging is being enabled.
Changes:
- clock.h: Replace 806MHz (0x2A) with 710.4MHz (0x25) based on 19.2MHz
XO.
- mainboard.c: Update handle_low_power_charging_boot() to use the
new L-VAL and update the debug log accordingly.
BUG=b:436391478
Change-Id: Ida30824e344a4613c797083711c3f6ee31f9694d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
During certain boot sequences, such as low-battery or off-mode charging,
automatic USB Type-C port resets initiated by the ADSP can cause
unnecessary power fluctuations or connectivity drops.
Implement adsp_skip_port_reset(), which toggles the SKIP_PORT_RESET bit
in the PMIC_PD_NEGOTIATION_FLAG register. This bit informs the ADSP
firmware to bypass its default port reset logic. Use this during
low-power charging initialization to ensure a more stable boot process.
BUG=b:436391478
TEST=Verify no unexpected port resets occur during Google/Quartz boot.
Change-Id: I215a1806799a10355dd36b483f8d441f615f5258
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91666
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds support to drop the CPU frequency to the minimum
806 MHz when the device enters OFF‑mode charging, improving power
efficiency. The register details are available in the
HRD-X1P42100-S1 hardware document:
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
Tested by creating an image.serial.bin and verifying that it boots
on X1P42100 and the CPU runs at 806 MHz during OFF‑mode charging.
Change-Id: I8f0d5b598a4dad419195957be8b334a27ec18982
Signed-off-by: Kirubakaran E <kirue@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91727
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Load ADSP firmware and then bring up LPASS/Q6 during the Bluey charging sequence.
This ensures ADSP‑dependent fast charging works reliably.
TEST:
- Built and booted image.serial.bin on X1P42100.
- Verified ADSP DTB and firmware load over UART.
- Verified Q6 and LPASS init during cold boot.
- Verified charging flow: device entered charging mode, battery current (~3550 mA)
reported, and CRD RED LED glowed.
Change-Id: I6a1326f4271c5121cd7284d64b2912505b2a93a2
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91564
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add clock_disable() (clear CBCR EN and poll CLK_OFF).
Add CBCR helper APIs and common bit definitions for HW_CTL,
FORCE_MEM_CORE_ON, IGNORE_RPMH_CLK_DIS and IGNORE_PMU_CLK_DIS.
BUG=None
TEST=Built and booted image.serial.bin on Bluey
Change-Id: I253414d01ec97aee45df1af0ed8cd06367351ef8
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91546
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
To support chargers connected through a Debug Accessory Mode (DAM)
cable, the PMIC must be configured to allow legacy charging paths even
when a debug accessory is detected.
Update the charging initialization to clear the suspend bit in the
SCHG_TYPE_C_SUSPEND_LEGACY_CHARGERS register. This ensures the SMB2360
can correctly negotiate and draw power when a DAM cable is in use.
BUG=none
TEST=Verify SMB2360 charging configuration on Google/Quartz.
Change-Id: I8d22abf92f4e8967efbe2ee3320c4a1461d6ef88
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91832
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Boost the initial CPU frequency from 1.36GHz to ~3.0GHz (2995.2 MHz)
during the boot phase to reduce the execution time of ramstage
and subsequent payload loading.
Changes:
- clock.h: Add L_VAL_2995P2MHz (0x9C) based on a 19.2MHz XO.
- clock.c: Update speed_up_boot_cpu() to use the 3.0GHz PLL
multiplier for the APSS NCC0 clock.
This change helps in further optimizing the boot timeline,
leveraging the higher clock speed for faster initialization.
BUG=b:449871690
TEST=Able to save ~50ms of the boot time (mostly during Qclib).
Change-Id: I459001717298b10201c3b3c8bf6b0c20097ae830
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91818
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Allow the SoC the specify the cache speed. Currently it's
always set to 0, which is unknown.
Change-Id: I317e248104c0026b7cca10b949fd47fba35b7338
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
On Qualcomm SoCs, the initial TTB is often placed in IMEM. During
ROMSTAGE, once DRAM is initialized and stable, the tables should be
moved to DRAM to ensure they remain accessible if IMEM is reclaimed
by other hardware blocks (like the ADSP).
Trigger mmu_relocate_ttb() at the end of the post-DRAM MMU
configuration flow.
BUG=b:436391478
TEST=Verify TTB moves to DRAM on Google/Quartz.
Debug logs:
```
[INFO ] Relocating TTB: 0x14842000 -> 0x80010000 (offset 0x6b7ce000)
[INFO ] TTB relocation is complete.
```
Change-Id: I123385e6cdd319c5ad4d3e7b266c506e7d2d5530
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91565
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Generate RAM ID for Samsung K4UBE3D4AA-MGCR
DRAM Part Name ID to assign
K4UBE3D4AA-MGCR 1 (0001)
BUG=b:420797833
BRANCH=firmware-brya-14505.B
TEST=emerge-constitution coreboot then check device boot
Change-Id: I9751baeec16d460b4d2b0de9158940e785ccf0ef
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91681
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Generate RAM ID for SCY SL5D32G32C2A-HC0
DRAM Part Name ID to assign
SL5D32G32C2A-HC0 3 (0011)
BUG=b:438402880
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot then check device boot
Change-Id: I354b950022cf05f69546d4c3d29f05981512ce51
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91519
Reviewed-by: Kyle Lin <kylelinck@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Before trying to use the SPI flash controller in ramstage or SMM check
if the bus can be claimed. If ROM Armor is enabled abort claiming the
bus. Sanity check as the caller must use PSP mailbox interface when
ROM Armor is enabled.
This commit introduces SOC_AMD_COMMON_BLOCK_PSP_ROM_ARMOR3, that will
be used in the following commits to active ROM Armor support.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: Id93747df92bfca46c15a1438c2804c0c574c9f99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add a function to return ROM Armor state from HSTI bits.
As soon as ROM Armor is enforced never check HSTI bits again
as it cannot be deactivated without a reboot.
TEST=Function returns 0 before running command
MBOX_BIOS_CMD_ARMOR_ENTER_SMM_MODE and returns 1 after
sending it to PSP.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: Ic9cf99b7f2461aa85fbd76998da5d035bf9e5ae3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91703
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The CPU Control Processor (CPUCP) requires a dedicated memory region
for firmware loading. Previously, accessing this region without
explicit MMU configuration could lead to suboptimal performance
during the transfer.
```
CPUCP Program Headers:
Type Offset VirtAddr PhysAddr
FileSiz MemSiz Flags Align
LOAD 0x0000000000001000 0x000000001cb00000 0x000000001cb00000
0x0000000000021d90 0x000000000002a630 RWE 0x1000
LOAD 0x0000000000023000 0x000000001cb2b000 0x000000001cb2b000
0x000000000000b570 0x000000000000b570 RW 0x1000
LOAD 0x000000000002f000 0x000000001cb3e000 0x000000001cb3e000
0x0000000000000890 0x0000000000000890 RW 0x1000
LOAD 0x0000000000000000 0x000000001cb3f000 0x000000001cb3f000
0x0000000000000000 0x0000000000001000 RW 0x1000
```
Key changes:
- symbols_common.h: Declare the 'cpucp' region.
- memlayout.ld: Define the CPUCP region at 0x1CB00000 (size 256K)
to align with SoC address maps.
- cpucp_load_reset.c: Map the CPUCP region as CACHED_RAM using
mmu_config_range() before loading the firmware.
- Flush and remap back the CPUCP range to device memory.
By ensuring the region is cached during the load and reset phase,
the firmware handoff is optimized, saving approximately 20ms of
overall boot time.
BUG=b:449871690
TEST=Able to save 20ms of the boot time.
Change-Id: I769f2cb7436ebfcc07eb2748b524066281a60a6e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The CPUCP (CPU Control Processor) firmware for X1P42100 is being
loaded as a payload. Compressing this file in CBFS can lead to
loading delays with the early-stage.
Set the compression type to 'none' to ensure the ELF is stored
uncompressed.
BUG=b:449871690
TEST=Able to optimize boot time (tested on google/quartz) by ~200ms.
w/o this patch:
```
fallback/cpucp 0xc7500 simple elf 149498 none
```
w/ this patch:
```
fallback/cpucp 0xc7500 simple elf 496196 none
```
Change-Id: I77418ac05ad950943a538ad1c2976d5cdfe41324
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Set defaults for VGA_BIOS_FILE and VGA_BIOS_ID.
TEST=Pre OS graphics init works on AMD/jaguar.
Change-Id: I3bf0e81b0de87abe4a03be8e10274936cf29e628
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
The function tlcl2_get_capability() is only linked when Kconfig TPM2
is being selected. Add a guard to not include the SMBIOS code when
TPM2 isn't selected.
TEST=Can compile the fTPM driver when TPM2 isn't selected.
Change-Id: I9385f15fc71c021f9be2bfb874898f76fa71fee4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91775
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These files use unit16_t and more, so this should be included.
Change-Id: If08dd6c3267b39cd72fcfaa9803c72260165337d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91815
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
drivers/intel/gma/opregion already provides a weak
mainboard_vbt_filename() implementation that returns "vbt.bin".
Drop the Starlabs overrides that return the same filename and keep only
the remaining board-specific override that still selects an alternate
VBT. This also removes the now-dead overrides left behind after
display-native-resolution VBT selection was dropped.
Change-Id: I89ec4f55d4c4ed3265a8d429c3d399977ad466d7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Allow the build system to specify the variable store position in flash
and update BIOS entry 0x6d when set.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: I3888810570897ea509a49fd4bc38d875d7d8be0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
When using ROM Armor, the AMD_BIOS_APOB_NV BIOS directory table
entry needs to be marked as writable. Add support for marking
BIOS directory table entries as writable and set all BIOS directory
files to RO, except for AMD_BIOS_APOB_NV (type 0x63), which is
written at end of coreboot based on the FMAP.
TEST=ROM Armor 3 enabled system can write APOB through PSP mailbox
interface. When the writable bit is not set cannot write APOB
through mailbox interface.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: Idce7f4afbdd2246a5c0fc96d27c3c721e4a5b03a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91700
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When ROM Armor is enabled and PSP is not in "capsule update mode",
the PSP can only write to PSP directory entries that have the writable
bit set. As the fTPM PSP trustlet must write to NVRAM regions as part
of the fTPM operation, set the writable bit on such regions.
Fixes crash on PSP side when using ROM Armor and fTPM.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: I5668976d687e5f9aa3fc62e91adf6bde5cadb5b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This removes the 'upcoming release' text and updates the statistics
for the 26.03 release tag.
Change-Id: Iecc233664d55b6b3b10a775a2990ec673b371754
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91782
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To comply with the Focal touchscreen module specification and prevent
interference during the power on init and self-calibration process,
the power-on sequence is implemented across different boot stages:
1. GPIO Initialization (Romstage/Ramstage):
- Pull Touch Enable (GPP_F08) High in the early GPIO table (Romstage)
to stabilize Vcc early.
- Pull Touch Report Switch (GPP_E05) High while initializing Touch
Reset (TCHSCR_RST_L, GPP_F16) to Low in the main GPIO table
(Ramstage) to maintain the reset state.
2. Chip Config Stage (Reset De-assertion):
- Implement fw_config_post_gpio_configure() to pull TCHSCR_RST_L High
during the BS_DEV_INIT_CHIPS stage.
- This ensures the reset is released only after Backlight (BL_ON) is
enabled, satisfying the module's calibration requirements.
3. ACPI & Power Management:
- Retain 'stop_gpio' (GPP_E05) in overridetree.cb for S0ix power
saving while removing 'reset_gpio' and 'enable_gpio' to avoid
driver conflicts with the manual boot sequence.
BUG=b:493322404
TEST=Build and boot on moonstone, verify touchscreen power-on
sequence with oscilloscope to match BOE requirements.
Verified on moonstone: Touchscreen is correctly detected and
functional after boot and S0ix resume.
Change-Id: I0fd323e56cd86ae85a40a489513e158b05be2233
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
