This patch adds a missing break statement in cbfstool's option parser.
This should reduce the chance of your bootblock file name suddenly
being a number after you swapped the order of some flags, and might save
you an hour of debugging and growing insanity.
Also removing a nearby empty line that looks out of place
BRANCH=None
BUG=None
TEST=Manual
Change-Id: I9beebdf29e4fc4aa645581146fdc61c659de72df
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/229973
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
This changes copies firmware version from vboot2 shared data to vboot1
shared data. This fixes FAFT firmware_TPMVersionCheck test.
BUG=none
BRANCH=ToT
TEST=firmware_TPMVersionCheck passed on Nyan Kitty.
Change-Id: Idfd282931421dc16cd1aa82c7ccb6c6790a4d0d7
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/230186
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Yen Lin <yelin@nvidia.com>
When displaying a 800x600 bitmap on 2560x1800 panel, the image
is shown very small. So, set the fb to 1280x800 (based on tegra
dsi driver default mode setting), a 800x600 image can be shown
relatively proportional to panel size.
BRANCH=none
BUG=chrome-os-partner:31936
TEST=build and test on ryu
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Change-Id: I62cbe9de1d1002293df20f8b1d752905c6ef33aa
Reviewed-on: https://chromium-review.googlesource.com/229912
Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Framebuffer line size and number of lines can have different
values than panel's resolution.
BRANCH=none
BUG=chrome-os-partner:31936
TEST=build and test on ryu
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Change-Id: Iedeef796f02286bb03920413420f8952cf34334a
Reviewed-on: https://chromium-review.googlesource.com/229915
Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
panel spec such as resoultion, bits per pixel are
needed to pass to depthcharge/payload for displaying
bitmap onto panel.
BRANCH=none
BUG=chrome-os-partner:31936
TEST=build and test on ryu
Change-Id: I5c8fde17d57e953582a1c1dc814be4c08e349847
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/227203
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
This should allow the max98090 codec to play beeps via
AHUB/I2S1 thru the depthcharge sound driver.
BUG=none
BRANCH=none
TEST=Saw max98090 codec init signon and register dump.
No sound yet.
Change-Id: I0bc8401e76b2c80a01083ac933a39f6cd4d1b78a
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/229496
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Mike Frysinger <vapier@chromium.org>
If all devices under AHUB (AUDIO/I2S/DAM/ADX/etc) aren't
clocked and taken out of reset, any access to any audio
peripheral will hang the system.
BUG=none
BRANCH=none
TEST=built both Rush and Ryu OK.
Change-Id: I741d5ba4dd8bd963b6d261fbf41cfb77c274cb79
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/229910
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Mike Frysinger <vapier@chromium.org>
Some actions are needed and some are not on the way resume from S3.
BRANCH=master
BUG=chrome-os-partner:33025,chrome-os-partner:33796
TEST=Built the image and confimed the boot_mode is correctly
configured.
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Change-Id: Ia042ea8c63c2306e9d6a80d8efa66c4fc0722d85
Reviewed-on: https://chromium-review.googlesource.com/229615
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Kenji Chen <kenji.chen@intel.com>
Tested-by: Kenji Chen <kenji.chen@intel.com>
I2C1 was missing in the funit/i2c/addressmap tables/code.
BUG=none
BRANCH=none
TEST=Built Rush and Ryu. Built Rush w/code in mainboard.c
to enable I2C1 for the MAX98090 audio codec - codec could be
read/written.
Change-Id: Ibe4f012fa2d427b95cd4672687132b47576b6a9a
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/229574
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This reverts commit e83de6429c.
The initialization can be moved into depthcharge. Moving it
there also provides symmetry with the backlight support.
BRANCH=none
BUG=chrome-os-partner:31936
TEST=built on ryu
Change-Id: I46e720567f5732f3a0e0612caa91670e8cb5aa8a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/229790
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Like most newer Chromebooks, Pinky and Jerry do not have physical
dev switches.
BUG=chrome-os-partner:33395
BRANCH=none
TEST=built and booted on Pinky, crossystem prints a valid value for
devsw_cur instead of an error.
Change-Id: I186518a59699d293c7938221b3ae45b27361c255
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/229680
Reviewed-by: Julius Werner <jwerner@chromium.org>
The TPS65913 PMIC has an RTC built into it. This change adds
a driver for it which implements the new RTC API.
BUG=chrome-os-partner:33764
BRANCH=None
TEST=Compiles and boots to kernel prompt on ryu. Timestamps for event log
verified across multiple boots.
Change-Id: If1d549ea2361d0de6be75fd24b9e9810a6df7457
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/229414
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
This patch adds support for Pinky rev3 (board ID 2) and Jerry rev2: the
power button GPIO changed polarity to low, the 5V_DRV pin for USB power
was moved to the AP again (welcome back!), and the EMMC_RST_L is now
finally on a port with the right IO voltage so we don't need any weird
pull-up tricks anymore. Since there are very few Jerry rev1s around,
we'll just move it over to the new code directly without introducing
board ID differences (also, because I have no idea how they stuffed it
this time... is this one actually called rev2?).
BRANCH=None
BUG=None
TEST=Still boots on my Pinky rev2, though that doesn't say much.
Change-Id: Iddee360fbda357ecde4ae5fbb5c3a01fe0c22474
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/229010
Reviewed-by: Lin Huang <hl@rock-chips.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This patch ports commit 567f616f (rk3288: slowly raise to max cpu
voltage to prevent overshoot) to Veyron_Jerry. It also fixes include
ordering and some comment grammar in the affected code.
BRANCH=None
BUG=chrome-os-partner:32716
TEST=None
Change-Id: I9c0aba40ddd8a0852391df184034baa740d063df
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/228938
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Stack and Timestamp need lesser than 2K and since romstage is running out of
memory, adjust the overall memory assignment.
BUG=chrome-os-partner:33676
BRANCH=None
TEST=Compiles and boots to kernel prompt.
Change-Id: I0134f25dd49f2940bb159d131aaee12f81e13ef7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/229001
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Commit-Queue: Tom Warren <twarren@nvidia.com>
Some USB sticks seem to send a NAK at a place where they mustn't
by spec, leading to a controller side error condition.
To avoid it, wait a millisecond which is enough to get past the
NAK condition. That delay only happens on device discovery so it
won't affect boot time by more than 1ms per device.
BUG=chromium:414959
BRANCH=none
TEST=depthcharge recognizes a Lexar 16GB USB stick after applying
this change.
Change-Id: I6dd5ca34e9f3767003ccb0ca9daaf16116f4a2df
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/228791
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
spi_flash->write returns non-zero on error and zero on success, not the
number of bytes written.
BUG=none
BRANCH=ToT
TEST=Booted storm. Verified successfully nvdata was saved.
Change-Id: If50cc1a62a4f06398d1830cca60085b6f925fff3
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/229389
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Provide support for SoCs to participate in PSCI
commands. There are 2 steps to a command:
1. prepare() - look at request and adjust state accordingly
2. commit() - take action on the command
The prepare() function is called with psci locks held while
the commit() function is called with the locks dropped. For
now, the one SoC doesn't implement the appropriate logic
yet.
BUG=chrome-os-partner:32136
BRANCH=None
TEST=Booted PSCI kernel -- no SMP because cmd_prepare()
knowingly fails. Spintable kernel still brings up both
CPUs.
Change-Id: I0821dc2ee8dc6bd1e8bc1c10f8b98b10e24fc97e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/226485
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Newly turned on CPUs need a place to go bring its EL3
state inline with expectations. Plumb this path in for
CPUs turning on as well as waking up from a power down
state. Some of the infrastructure declarations were
moved around for easier consumption in ramstage and
secmon. Lastly, a psci_soc_init() is added to
inform the SoC of the CPU's entry point as well do
any initialization.
BUG=chrome-os-partner:32112
BRANCH=None
TEST=Built and booted. On entry point not actually utilized.
Change-Id: I7b8c8c828ffb73752ca3ac1117cd895a5aa275d8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/228296
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
It can't compile due to tpmp flag was removed in nvs.h
BRANCH=none
BUG=none
TEST=compile ok and boot to OS on pearlvalley
Signed-off-by: Kane Chen <kane.chen@intel.com>
Change-Id: I718b70c6194365ee19b93224b52b7bcf3a5055d0
Reviewed-on: https://chromium-review.googlesource.com/228975
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Kane Chen <kane.chen@intel.com>
Tested-by: Kane Chen <kane.chen@intel.com>
Enable display only developer and recovery mode.
Will add in the actual display supporting functions in coming
patches.
BRANCH=none
BUG=chrome-os-partner:31936
TEST=build and test on ryu
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Change-Id: Idfa24d23c81baaedb944d2b9835255edad4e422b
Reviewed-on: https://chromium-review.googlesource.com/226904
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
1. Add page address, an i2c address, into register address table
2. Add pmic read function
3. Add more registers and setting values.
BRANCH=none
BUG=chrome-os-partner:31936
TEST=build and test on ryu
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Change-Id: I227b3e9390e6fc020707d4730c19945760df6ca2
Reviewed-on: https://chromium-review.googlesource.com/226902
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com>
Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
This enables RAM_CODE_SUPPORT for veyron* platforms and uses the
generic gpio_get_binaries() function to read RAM_ID GPIOs.
BUG=chrome-os-partner:31728
BRANCH=none
TEST=built and booted on pinky
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Ibc4c61687f1c59311cbf6b48371f9a9125dbe115
Reviewed-on: https://chromium-review.googlesource.com/227249
Reviewed-by: Julius Werner <jwerner@chromium.org>
Take codec out of reset (GPIO_PH1 aka CODEC_RST_L) and enable LDO2
(GPIO_PR2/KB_ROW2 aka AUDIO_ENABLE). Muxes are setup and the two
GPIOs are set to output and driven high.
BUG=chrome-os-partner:32582
BRANCH=none
TEST=RealTek ALC5677 codec shows up in I2C6 scan at address 0x2D,
can read/write registers.
Change-Id: Iedce7bb9f8e61d3b8cd693fc5e567323d89f8046
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/228920
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Proto 0,1,2 boards had pwr btn active high. Proto 3 onwards boards will have pwr
btn active low. Thus, select power btn polarity based on board id.
BUG=chrome-os-partner:33545
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt on ryu proto 1.
Change-Id: Icdf51b9324385de00f5787e81018518c5397215f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/229011
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
This adds the RAM config code to the coreboot tables. The purpose is
to expose this information to software running at higher levels, e.g.
to print the RAM config coreboot is using as part of factory tests.
The prototype for ram_code() is in boardid.h since they are closely
related and will likely have common code.
BUG=chrome-os-partner:31728
BRANCH=none
TEST=tested w/ follow-up CLs on pinky
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Idd38ec5b6af16e87dfff2e3750c18fdaea604400
Reviewed-on: https://chromium-review.googlesource.com/227248
Reviewed-by: Julius Werner <jwerner@chromium.org>
This will be connected to the coded for firmware upload.
BUG=chrome-os-partner:33495
BRANCH=samus
TEST=build and boot on samus, check that GSPI driver is loaded
Change-Id: I25c91145aef8ca2aef229ffb27e8a45df659982e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/228835
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Switched to CRC 16 as it's 40% faster than CRC x25.
Both CRC 16 and CRC x25 are supported and either can be selected through
define directives.
BUG=chrome-os-partner:31438
TEST=built urara bootblock and verified content of bootblock.bin, observed
expected content; ran it on Pistachio FPGA and observed that its
content is read properly by bootrom.
BRANCH=none
Change-Id: If1a78350e0b48d91bfe64ead45f852f44ba3cf9a
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://chromium-review.googlesource.com/226840
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
When the driver is included in bootblock, malloc() is not available.
Come to think of it, it is perfectly fine to use a statically
allocated structure for the SPI device descriptor - coreboot is
unlikely to require concurrent support of multiple SPI devices of the
same kind.
BRANCH=none
BUG=chrome-os-partner:31438
TEST=bootblock on the FPGA board recognizes the installed Winbond
device:
coreboot-4.0 bootblock Tue Nov 11 07:27:24 PST 2014 starting...
SF: Detected W25Q16 with page size 1000, total 200000
Change-Id: Iaa69d610ef18e69b1ae5ade2d958f9fe1595a723
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/228959
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is a (hopefully temporary) workaround for some bad panels
that do not work unless we have extra delay before running the
option rom.
BUG=chrome-os-partner:33671
BRANCH=samus
TEST=build and boot on samus with 'bad' panel and ensure that
the panel is always (50/50 times) brought up in developer and
recovery modes.
Change-Id: Ife779803c89ff56ff9b50e6b7c7c022300062a63
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/228883
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This changes the broadwell graphics init path to only do the delay
before initializing graphics when running chromeos if we are also
going to execute the option rom.
BUG=chrome-os-partner:33671
BRANCH=samus
TEST=build and boot on samus
Change-Id: I350f85738efe3d17152de4f025adbfd52ae15b95
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/228882
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
