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jecht: port/merge panther and auron BSP code

Browse source 
Port and merge panther BSP code into auron base, to create jecht.

BUG=None
TEST=None
BRANCH=None

Change-Id: Ib60241fefb1ea67708af24bf22d4305492d1306f
Signed-off-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/227706
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
This commit is contained in:
Wenkai Du 2014-11-05 17:29:36 -08:00 • committed by chrome-internal-fetch
commit 899720fc39
26 changed files with 618 additions and 924 deletions
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3
src/mainboard/google/jecht/Kconfig
View file

@ -4,8 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select SOC_INTEL_BROADWELL
select BOARD_ROMSIZE_KB_8192
select EC_GOOGLE_CHROMEEC
select EC_SOFTWARE_SYNC
select SUPERIO_ITE_IT8772F
select VIRTUAL_DEV_SWITCH
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE

4
src/mainboard/google/jecht/Makefile.inc
View file

@ -18,11 +18,9 @@
##
subdirs-y += spd
ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-y += lan.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c

24
src/mainboard/google/jecht/acpi/ec.asl
View file

@ -1,24 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* mainboard configuration */
#include <mainboard/google/jecht/ec.h>
/* ACPI code for EC functions */
#include <ec/google/chromeec/acpi/ec.asl>

191
src/mainboard/google/jecht/acpi/mainboard.asl
View file

@ -23,21 +23,6 @@
Scope (\_SB)
{
Device (LID0)
{
Name(_HID, EisaId("PNP0C0D"))
Method(_LID, 0)
{
Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS)
Return (\LIDS)
}
// There is no GPIO for LID, the EC pulses WAKE# pin instead.
// There is no GPE for WAKE#, so fake it with PCI_EXP_WAKE
Name (_PRW, Package(){ 0x69, 5 }) // PCI_EXP
}
Device (PWRB)
{
Name(_HID, EisaId("PNP0C0C"))
@ -52,184 +37,46 @@ Scope (\_SB.PCI0.LPCB)
#include <drivers/pc80/tpm/acpi/tpm.asl>
}
Scope (\_SB.PCI0.I2C0)
/*
* LAN connected to Root Port 3, becomes Root Port 1 after coalesce
*/
Scope (\_SB.PCI0.RP01)
{
Device (ETPA)
Device (ETH0)
{
Name (_HID, "ELAN0000")
Name (_DDN, "Elan Touchpad")
Name (_UID, 1)
Name (ISTP, 1) /* Touchpad */
Name (_CRS, ResourceTemplate()
{
I2cSerialBus (
0x15, // SlaveAddress
ControllerInitiated, // SlaveMode
400000, // ConnectionSpeed
AddressingMode7Bit, // AddressingMode
"\\_SB.PCI0.I2C0", // ResourceSource
)
Interrupt (ResourceConsumer, Edge, ActiveLow)
{
BOARD_TRACKPAD_IRQ
}
})
Method (_STA)
{
If (LEqual (\S1EN, 1)) {
Return (0xF)
} Else {
Return (0x0)
}
}
Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
Name (_ADR, 0x00000000)
Name (_PRW, Package() { PANTHER_NIC_WAKE_GPIO, 3 })
Method (_DSW, 3, NotSerialized)
{
Store (BOARD_TRACKPAD_WAKE_GPIO, Local0)
Store (PANTHER_NIC_WAKE_GPIO, Local0)
If (LEqual (Arg0, 1)) {
// Enable GPIO as wake source
\_SB.PCI0.LPCB.GPIO.GWAK (Local0)
}
}
/* Allow device to power off in S0 */
Name (_S0W, 4)
}
Device (CTPA)
{
Name (_HID, "CYAP0000")
Name (_DDN, "Cypress Touchpad")
Name (_UID, 3)
Name (ISTP, 1) /* Touchpad */
Name (_CRS, ResourceTemplate()
{
I2cSerialBus (
0x67, // SlaveAddress
ControllerInitiated, // SlaveMode
400000, // ConnectionSpeed
AddressingMode7Bit, // AddressingMode
"\\_SB.PCI0.I2C0", // ResourceSource
)
Interrupt (ResourceConsumer, Edge, ActiveLow)
{
BOARD_TRACKPAD_IRQ
}
})
Method (_STA)
{
If (LEqual (\S1EN, 1)) {
Return (0xF)
} Else {
Return (0x0)
}
}
Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
Method (_DSW, 3, NotSerialized)
{
Store (BOARD_TRACKPAD_WAKE_GPIO, Local0)
If (LEqual (Arg0, 1)) {
// Enable GPIO as wake source
\_SB.PCI0.LPCB.GPIO.GWAK (Local0)
}
}
/* Allow device to power off in S0 */
Name (_S0W, 4)
}
}
Scope (\_SB.PCI0.I2C1)
/*
* WLAN connected to Root Port 4, becomes Root Port 2 after coalesce
*/
Scope (\_SB.PCI0.RP02)
{
Device (ATSA)
Device (WLAN)
{
Name (_HID, "ATML0001")
Name (_DDN, "Atmel Touchscreen")
Name (_UID, 5)
Name (_S0W, 4)
Name (ISTP, 0) /* TouchScreen */
Name (_CRS, ResourceTemplate()
{
I2cSerialBus (
0x4a, // SlaveAddress
ControllerInitiated, // SlaveMode
400000, // ConnectionSpeed
AddressingMode7Bit, // AddressingMode
"\\_SB.PCI0.I2C1", // ResourceSource
)
// GPIO54 (ball L3) is PIRQW: PIRQL_GSI + PIRQL - PIRQW = PIRQW_GSI
// 27 + 3 - 14 = 38
Interrupt (ResourceConsumer, Edge, ActiveLow) { 38 }
})
Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 })
Name (_ADR, 0x00000000)
Name (_PRW, Package() { PANTHER_WLAN_WAKE_GPIO, 3 })
Method (_DSW, 3, NotSerialized)
{
Store (BOARD_TOUCHSCREEN_WAKE_GPIO, Local0)
Store (PANTHER_WLAN_WAKE_GPIO, Local0)
If (LEqual (Arg0, 1)) {
// Enable GPIO as wake source
\_SB.PCI0.LPCB.GPIO.GWAK (Local0)
}
}
Method (_STA)
{
If (LEqual (\S2EN, 1)) {
Return (0xF)
} Else {
Return (0x0)
}
}
}
Device (ALSI)
{
/*
* TODO(dlaurie): Need official HID.
*
* The current HID is created from the Intersil PNP
* Vendor ID "LSD" and a shortened device identifier.
*/
Name (_HID, EisaId ("LSD2918"))
Name (_DDN, "Intersil 29018 Ambient Light Sensor")
Name (_UID, 6)
Name (_CRS, ResourceTemplate()
{
I2cSerialBus (
0x44, // SlaveAddress
ControllerInitiated, // SlaveMode
400000, // ConnectionSpeed
AddressingMode7Bit, // AddressingMode
"\\_SB.I2C1", // ResourceSource
)
// On Jecht/Peppy board, IRQ is hooked to GPIO 51.
// Based on table 5-36, this is PIRQT. Then based on
// table 5-12, this is IRQ #35.
Interrupt (ResourceConsumer, Edge, ActiveLow)
{
35
}
})
Method (_STA)
{
If (LEqual (\S2EN, 1)) {
Return (0xF)
} Else {
Return (0x0)
}
}
}
}

25
src/mainboard/google/jecht/acpi/superio.asl
View file

@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2012 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -17,13 +17,20 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* mainboard configuration */
#include <mainboard/google/jecht/ec.h>
/* Values should match those defined in devicetree.cb */
#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources
#define SIO_EC_HOST_ENABLE // EC Host Interface Resources
#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
#define SIO_EC_ENABLE_COM1 // Enable Serial Port 1
#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller
#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR
#define SIO_ENABLE_PS2K // pnp 2e.5: Enable PS/2 Keyboard
#define SIO_ENABLE_PS2M // pnp 2e.6: Enable PS/2 Mouse
#define SIO_ENABLE_COM1 // pnp 2e.1: Enable Serial Port 1
#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller
#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60
#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62
#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO
#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60
#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60
#include "superio/ite/it8772f/acpi/superio.asl"
/* ACPI code for EC SuperIO functions */
#include <ec/google/chromeec/acpi/superio.asl>

49
src/mainboard/google/jecht/acpi/thermal.asl
View file

@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2014 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -63,53 +63,48 @@ Scope (\_TZ)
Method (TCHK, 0, Serialized)
{
// Get Temperature from TIN# set in NVS
Store (\_SB.PCI0.LPCB.EC0.TINS (TMPS), Local0)
// Get CPU Temperature from PECI via SuperIO TMPIN3
Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0)
// Check for sensor not calibrated
If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNCA)) {
Return (CTOK(0))
// Check for "no reading available
If (LEqual (Local0, 0x80)) {
Return (CTOK (0))
}
// Check for sensor not present
If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) {
Return (CTOK(0))
// Check for invalid readings
If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) {
Return (CTOK (0))
}
// Check for sensor not powered
If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) {
Return (CTOK(0))
// PECI raw value is an offset from Tj_max
Subtract (255, Local0, Local1)
// Handle values greater than Tj_max
If (LGreaterEqual (Local1, \TMAX)) {
Return (CTOK (0))
}
// Check for sensor bad reading
If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) {
Return (CTOK(0))
}
// Adjust by offset to get Kelvin
Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0)
// Convert to 1/10 Kelvin
Multiply (Local0, 10, Local0)
Return (Local0)
// Subtract from Tj_max to get temperature
Subtract (\TMAX, Local1, Local0)
Return (CTOK (Local0))
}
Method (_TMP, 0, Serialized)
{
// Get temperature from EC in deci-kelvin
// Get temperature from SuperIO in deci-kelvin
Store (TCHK (), Local0)
// Critical temperature in deci-kelvin
Store (CTOK (\TCRT), Local1)
Store (CTOK (\TMAX), Local1)
If (LGreaterEqual (Local0, Local1)) {
Store ("CRITICAL TEMPERATURE", Debug)
Store (Local0, Debug)
// Wait 1 second for EC to re-poll
// Wait 1 second for SuperIO to re-poll
Sleep (1000)
// Re-read temperature from EC
// Re-read temperature from SuperIO
Store (TCHK (), Local0)
Store ("RE-READ TEMPERATURE", Debug)

75
src/mainboard/google/jecht/chromeos.c
View file

@ -25,23 +25,20 @@
#include <vendorcode/google/chromeos/chromeos.h>
#include <ec/google/chromeec/ec.h>
#include <soc/gpio.h>
#include "ec.h"
#include <soc/sata.h>
/* SPI Write protect is GPIO 16 */
#define CROS_WP_GPIO 58
#define GPIO_SPI_WP 58
#define GPIO_REC_MODE 12
#define FLAG_SPI_WP 0
#define FLAG_REC_MODE 1
#define FLAG_DEV_MODE 2
#ifndef __PRE_RAM__
#include <boot/coreboot_tables.h>
#define GPIO_COUNT 6
static int get_lid_switch(void)
{
u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES);
return !!(ec_switches & EC_SWITCH_LID_OPEN);
}
static void fill_lb_gpio(struct lb_gpio *gpio, int num,
int polarity, const char *name, int force)
{
@ -63,43 +60,59 @@ void fill_lb_gpios(struct lb_gpios *gpios)
gpios->count = GPIO_COUNT;
gpio = gpios->gpios;
fill_lb_gpio(gpio++, CROS_WP_GPIO, ACTIVE_HIGH, "write protect", 0);
fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery",
fill_lb_gpio(gpio++, GPIO_SPI_WP, ACTIVE_HIGH, "write protect", 0);
fill_lb_gpio(gpio++, GPIO_REC_MODE, ACTIVE_LOW, "recovery",
get_recovery_mode_switch());
fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer",
get_developer_mode_switch());
fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid",
get_lid_switch());
fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", 1);
fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0);
fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", oprom_is_loaded);
}
#endif
/* The dev-switch is virtual */
int get_write_protect_state(void)
{
device_t dev;
#ifdef __PRE_RAM__
dev = PCI_DEV(0, 0x1f, 2);
#else
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
#endif
return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
}
int get_developer_mode_switch(void)
{
return 0;
}
/* There are actually two recovery switches. One is the magic keyboard chord,
* the other is driven by Servo. */
int get_recovery_mode_switch(void)
{
u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES);
u32 ec_events;
/* If a switch is set, we don't need to look at events. */
if (ec_switches & (EC_SWITCH_DEDICATED_RECOVERY))
return 1;
/* Else check if the EC has posted the keyboard recovery event. */
ec_events = google_chromeec_get_events_b();
return !!(ec_events &
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
device_t dev;
#ifdef __PRE_RAM__
dev = PCI_DEV(0, 0x1f, 2);
#else
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
#endif
return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;
}
int get_write_protect_state(void)
#ifdef __PRE_RAM__
void save_chromeos_gpios(void)
{
return get_gpio(CROS_WP_GPIO);
u32 flags = 0;
/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */
if (get_gpio(GPIO_SPI_WP))
flags |= (1 << FLAG_SPI_WP);
/* Recovery: GPIO12 = RECOVERY_L, active low */
if (!get_gpio(GPIO_REC_MODE))
flags |= (1 << FLAG_REC_MODE);
/* Developer: Virtual */
pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
}
#endif

106
src/mainboard/google/jecht/devicetree.cb
View file

@ -1,25 +1,16 @@
chip soc/intel/broadwell
# Enable eDP Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
# Disable eDP Hotplug
register "gpu_dp_d_hotplug" = "0x00"
# Disable DisplayPort C Hotplug
register "gpu_dp_c_hotplug" = "0x00"
# Enable DisplayPort C Hotplug with 6ms pulse
register "gpu_dp_c_hotplug" = "0x06"
# Enable HDMI Hotplug with 6ms pulse
register "gpu_dp_b_hotplug" = "0x06"
# Set backlight PWM values for eDP
register "gpu_cpu_backlight" = "0x00000200"
register "gpu_pch_backlight" = "0x04000000"
# Enable Panel and configure power delays
register "gpu_panel_port_select" = "1" # eDP
register "gpu_panel_power_cycle_delay" = "5" # 400ms
register "gpu_panel_power_up_delay" = "400" # 40ms
register "gpu_panel_power_down_delay" = "150" # 15ms
register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
register "pirqa_routing" = "0x8b"
register "pirqb_routing" = "0x8a"
@ -30,32 +21,30 @@ chip soc/intel/broadwell
register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x80"
# EC range is 0x800-0x9ff
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x00fc0901"
# SuperIO range is 0x700-0x73f
register "gen2_dec" = "0x003c0701"
# EC_SMI is GPIO34
register "alt_gp_smi_en" = "0x0004"
register "alt_gp_smi_en" = "0x0000"
register "gpe0_en_1" = "0x00000000"
# EC_SCI is GPIO36
register "gpe0_en_2" = "0x00000010"
register "gpe0_en_2" = "0x00000000"
register "gpe0_en_3" = "0x00000000"
register "gpe0_en_4" = "0x00000000"
register "sata_port_map" = "0x1"
register "sio_acpi_mode" = "1"
register "sata_devslp_disable" = "0x1"
# DTLE DATA / EDGE values
register "sata_port0_gen3_dtle" = "0x5"
register "sata_port1_gen3_dtle" = "0x5"
register "sio_acpi_mode" = "0"
register "sio_i2c0_voltage" = "0" # 3.3V
register "sio_i2c1_voltage" = "0" # 3.3V
# Force enable ASPM for PCIe Port1
register "pcie_port_force_aspm" = "0x01"
# Force enable ASPM for PCIe Port 4
register "pcie_port_force_aspm" = "0x10"
# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
register "icc_clock_disable" = "0x013c0000"
# Enable port coalescing
register "pcie_port_coalesce" = "1"
register "s0ix_enable" = "1"
# Disable PCIe CLKOUT 1,5 and CLKOUT_XDP
register "icc_clock_disable" = "0x01220000"
device cpu_cluster 0 on
device lapic 0 on end
@ -67,9 +56,9 @@ chip soc/intel/broadwell
device pci 03.0 on end # mini-hd audio
device pci 13.0 off end # Smart Sound Audio DSP
device pci 14.0 on end # USB3 XHCI
device pci 15.0 on end # Serial I/O DMA
device pci 15.1 on end # I2C0
device pci 15.2 on end # I2C1
device pci 15.0 off end # Serial I/O DMA
device pci 15.1 off end # I2C0
device pci 15.2 off end # I2C1
device pci 15.3 off end # GSPI0
device pci 15.4 off end # GSPI1
device pci 15.5 off end # UART0
@ -81,28 +70,53 @@ chip soc/intel/broadwell
device pci 17.0 off end # SDIO
device pci 19.0 off end # GbE
device pci 1b.0 on end # High Definition Audio
device pci 1c.0 on end # PCIe Port #1
device pci 1c.0 off end # PCIe Port #1
device pci 1c.1 off end # PCIe Port #2
device pci 1c.2 off end # PCIe Port #3
device pci 1c.3 off end # PCIe Port #4
device pci 1c.4 off end # PCIe Port #5
device pci 1c.2 on end # PCIe Port #3
device pci 1c.3 on end # PCIe Port #4
device pci 1c.4 on end # PCIe Port #5
device pci 1c.5 off end # PCIe Port #6
device pci 1d.0 on end # USB2 EHCI
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on
chip drivers/pc80/tpm
# Rising edge interrupt
register "irq_polarity" = "2"
device pnp 0c31.0 on
irq 0x70 = 10
chip superio/ite/it8772f
# Skip keyboard init
register "skip_keyboard" = "1"
# Enable PECI on TMPIN3
register "peci_tmpin" = "3"
# Enable FAN2
register "fan2_enable" = "1"
device pnp 2e.0 off end # FDC
device pnp 2e.1 on # Serial Port 1
io 0x60 = 0x3f8
irq 0x70 = 4
end
end
chip ec/google/chromeec
device pnp 0c09.0 on end
device pnp 2e.4 on # Environment Controller
io 0x60 = 0x700
io 0x62 = 0x710
irq 0x70 = 0x09
irq 0xf2 = 0x20
irq 0xf4 = 0x0
irq 0xfa = 0x12
end
device pnp 2e.7 on # GPIO
io 0x60 = 0x720
io 0x62 = 0x730
end
device pnp 2e.5 on
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
end # Keyboard
device pnp 2e.6 on
irq 0x70 = 12
end # Mouse
device pnp 2e.a off end # IR
end
end # LPC bridge
device pci 1f.2 on end # SATA Controller
device pci 1f.3 off end # SMBus
device pci 1f.3 on end # SMBus
device pci 1f.6 on end # Thermal
end
end

53
src/mainboard/google/jecht/ec.c
View file

@ -1,53 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/acpi.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <types.h>
#include <console/console.h>
#include <ec/google/chromeec/ec.h>
#include "ec.h"
void mainboard_ec_init(void)
{
printk(BIOS_DEBUG, "mainboard_ec_init\n");
post_code(0xf0);
/* Restore SCI event mask on resume. */
if (acpi_slp_type == 3) {
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
MAINBOARD_EC_S3_WAKE_EVENTS);
/* Disable SMI and wake events */
google_chromeec_set_smi_mask(0);
/* Clear pending events */
while (google_chromeec_get_event() != 0)
;
google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
} else {
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
MAINBOARD_EC_S5_WAKE_EVENTS);
}
/* Clear wake events, these are enabled on entry to sleep */
google_chromeec_set_wake_mask(0);
post_code(0xf1);
}

65
src/mainboard/google/jecht/ec.h
View file

@ -1,65 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef MAINBOARD_EC_H
#define MAINBOARD_EC_H
#include <ec/google/chromeec/ec_commands.h>
#define EC_SCI_GPI 36 /* GPIO36 is EC_SCI# */
#define EC_SMI_GPI 34 /* GPIO34 is EC_SMI# */
#define MAINBOARD_EC_SCI_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER))
#define MAINBOARD_EC_SMI_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
/* EC can wake from S5 with lid or power button */
#define MAINBOARD_EC_S5_WAKE_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
/* EC can wake from S3 with lid or power button or key press */
#define MAINBOARD_EC_S3_WAKE_EVENTS \
(MAINBOARD_EC_S5_WAKE_EVENTS |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
/* Log EC wake events plus EC shutdown events */
#define MAINBOARD_EC_LOG_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN))
#ifndef __ACPI__
extern void mainboard_ec_init(void);
#endif
#endif

109
src/mainboard/google/jecht/fadt.c
View file

@ -19,11 +19,16 @@
*/
#include <string.h>
#include <device/pci.h>
#include <soc/acpi.h>
#include <cpu/x86/smm.h>
#include <soc/pch.h>
#include <soc/iomap.h>
void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
{
acpi_header_t *header = &(fadt->header);
u16 pmbase = ACPI_BASE_ADDRESS;
memset((void *) fadt, 0, sizeof(acpi_fadt_t));
memcpy(header->signature, "FACP", 4);
@ -39,12 +44,114 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
fadt->model = 1;
fadt->preferred_pm_profile = PM_MOBILE;
fadt->sci_int = 0x9;
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = 0;
fadt->pm1a_evt_blk = pmbase;
fadt->pm1b_evt_blk = 0x0;
fadt->pm1a_cnt_blk = pmbase + 0x4;
fadt->pm1b_cnt_blk = 0x0;
fadt->pm2_cnt_blk = pmbase + 0x50;
fadt->pm_tmr_blk = pmbase + 0x8;
fadt->gpe0_blk = pmbase + 0x80;
fadt->gpe1_blk = 0;
fadt->pm1_evt_len = 4;
fadt->pm1_cnt_len = 2;
fadt->pm2_cnt_len = 1;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 32;
fadt->gpe1_blk_len = 0;
fadt->gpe1_base = 0;
fadt->cst_cnt = 0;
fadt->p_lvl2_lat = 1;
fadt->p_lvl3_lat = 87;
fadt->flush_size = 1024;
fadt->flush_stride = 16;
fadt->duty_offset = 1;
fadt->duty_width = 0;
fadt->day_alrm = 0xd;
fadt->mon_alrm = 0x00;
fadt->century = 0x00;
fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
fadt->reset_reg.space_id = 1;
fadt->reset_reg.bit_width = 8;
fadt->reset_reg.bit_offset = 0;
fadt->reset_reg.resv = 0;
fadt->reset_reg.addrl = 0xcf9;
fadt->reset_reg.addrh = 0;
fadt->reset_value = 6;
fadt->x_firmware_ctl_l = (unsigned long)facs;
fadt->x_firmware_ctl_h = 0;
fadt->x_dsdt_l = (unsigned long)dsdt;
fadt->x_dsdt_h = 0;
acpi_fill_in_fadt(fadt);
fadt->x_pm1a_evt_blk.space_id = 1;
fadt->x_pm1a_evt_blk.bit_width = 32;
fadt->x_pm1a_evt_blk.bit_offset = 0;
fadt->x_pm1a_evt_blk.resv = 0;
fadt->x_pm1a_evt_blk.addrl = pmbase;
fadt->x_pm1a_evt_blk.addrh = 0x0;
fadt->x_pm1b_evt_blk.space_id = 1;
fadt->x_pm1b_evt_blk.bit_width = 0;
fadt->x_pm1b_evt_blk.bit_offset = 0;
fadt->x_pm1b_evt_blk.resv = 0;
fadt->x_pm1b_evt_blk.addrl = 0x0;
fadt->x_pm1b_evt_blk.addrh = 0x0;
fadt->x_pm1a_cnt_blk.space_id = 1;
fadt->x_pm1a_cnt_blk.bit_width = 16;
fadt->x_pm1a_cnt_blk.bit_offset = 0;
fadt->x_pm1a_cnt_blk.resv = 0;
fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
fadt->x_pm1a_cnt_blk.addrh = 0x0;
fadt->x_pm1b_cnt_blk.space_id = 1;
fadt->x_pm1b_cnt_blk.bit_width = 0;
fadt->x_pm1b_cnt_blk.bit_offset = 0;
fadt->x_pm1b_cnt_blk.resv = 0;
fadt->x_pm1b_cnt_blk.addrl = 0x0;
fadt->x_pm1b_cnt_blk.addrh = 0x0;
fadt->x_pm2_cnt_blk.space_id = 1;
fadt->x_pm2_cnt_blk.bit_width = 8;
fadt->x_pm2_cnt_blk.bit_offset = 0;
fadt->x_pm2_cnt_blk.resv = 0;
fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
fadt->x_pm2_cnt_blk.addrh = 0x0;
fadt->x_pm_tmr_blk.space_id = 1;
fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.resv = 0;
fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
fadt->x_pm_tmr_blk.addrh = 0x0;
fadt->x_gpe0_blk.space_id = 0;
fadt->x_gpe0_blk.bit_width = 0;
fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.resv = 0;
fadt->x_gpe0_blk.addrl = 0;
fadt->x_gpe0_blk.addrh = 0x0;
fadt->x_gpe1_blk.space_id = 1;
fadt->x_gpe1_blk.bit_width = 0;
fadt->x_gpe1_blk.bit_offset = 0;
fadt->x_gpe1_blk.resv = 0;
fadt->x_gpe1_blk.addrl = 0x0;
fadt->x_gpe1_blk.addrh = 0x0;
header->checksum =
acpi_checksum((void *) fadt, header->length);

70
src/mainboard/google/jecht/gpio.h
View file

@ -31,31 +31,31 @@ static const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */
PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */
PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */
PCH_GPIO_ACPI_SCI, /* 8: LTE_WAKE_L_Q */
PCH_GPIO_INPUT, /* 9: RAM_ID1 */
PCH_GPIO_ACPI_SCI, /* 8: LAN_WAKE_L_Q */
PCH_GPIO_OUT_HIGH, /* 9: PP3300_WLAN_EN */
PCH_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */
PCH_GPIO_UNUSED, /* 11: UNUSED */
PCH_GPIO_INPUT_INVERT, /* 12: TRACKPAD_INT_L (WAKE) */
PCH_GPIO_INPUT, /* 13: RAM_ID0 */
PCH_GPIO_INPUT, /* 14: EC_IN_RW */
PCH_GPIO_UNUSED, /* 11: SMBALERT */
PCH_GPIO_INPUT_INVERT, /* 12: RECOVERY_L */
PCH_GPIO_UNUSED, /* 13: UNUSED */
PCH_GPIO_UNUSED, /* 14: UNUSED */
PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */
PCH_GPIO_UNUSED, /* 16: UNUSED */
PCH_GPIO_UNUSED, /* 17: UNUSED */
PCH_GPIO_NATIVE, /* 18: PCIE_CLKREQ_WLAN# */
PCH_GPIO_OUT_HIGH, /* 17: PP3300_VP8_EN */
PCH_GPIO_UNUSED, /* 18: UNUSED */
PCH_GPIO_UNUSED, /* 19: UNUSED */
PCH_GPIO_UNUSED, /* 20: UNUSED */
PCH_GPIO_UNUSED, /* 21: UNUSED */
PCH_GPIO_UNUSED, /* 22: UNUSED */
PCH_GPIO_NATIVE, /* 20: NATIVE: CLK_PCIE_REQ2# */
PCH_GPIO_NATIVE, /* 21: NATIVE: CLK_PCIE_REQ3# */
PCH_GPIO_NATIVE, /* 22: NATIVE: CLK_PCIE_REQ4# */
PCH_GPIO_UNUSED, /* 23: UNUSED */
PCH_GPIO_UNUSED, /* 24: UNUSED */
PCH_GPIO_INPUT_INVERT, /* 25: TOUCH_INT_L (WAKE) */
PCH_GPIO_UNUSED, /* 26: UNUSED */
PCH_GPIO_OUT_HIGH, /* 24: WLAN_OFF_L */
PCH_GPIO_UNUSED, /* 25: UNUSED */
PCH_GPIO_OUT_HIGH, /* 26: USB_CTL_1 */
PCH_GPIO_UNUSED, /* 27: UNUSED */
PCH_GPIO_UNUSED, /* 28: UNUSED */
PCH_GPIO_OUT_LOW, /* 28: USB_ILIM_SEL */
PCH_GPIO_UNUSED, /* 29: UNUSED */
PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */
PCH_GPIO_NATIVE, /* 31: NATIVE: ACPRESENT */
PCH_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */
PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSPWRACK_L */
PCH_GPIO_NATIVE, /* 31: NATIVE: PCH_ACPRESENT */
PCH_GPIO_NATIVE, /* 32: NATIVE: CLKRUN# */
PCH_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */
PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */
PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */
@ -64,26 +64,26 @@ static const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_UNUSED, /* 38: UNUSED */
PCH_GPIO_UNUSED, /* 39: UNUSED */
PCH_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */
PCH_GPIO_UNUSED, /* 41: UNUSED */
PCH_GPIO_NATIVE, /* 41: NATIVE: USB_OC1# */
PCH_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */
PCH_GPIO_UNUSED, /* 43: UNUSED */
PCH_GPIO_OUT_HIGH, /* 44: PP3300_SSD_EN */
PCH_GPIO_OUT_HIGH, /* 45: PP3300_CODEC_EN */
PCH_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */
PCH_GPIO_INPUT, /* 47: RAM_ID2 */
PCH_GPIO_NATIVE, /* 43: NATIVE: USB_OC3# */
PCH_GPIO_UNUSED, /* 44: UNUSED */
PCH_GPIO_OUT_HIGH, /* 45: PP5000_CODEC_EN */
PCH_GPIO_OUT_HIGH, /* 46: BT_DISABLE_L */
PCH_GPIO_OUT_HIGH, /* 47: USB1_PWR_EN */
PCH_GPIO_UNUSED, /* 48: UNUSED */
PCH_GPIO_UNUSED, /* 49: UNUSED */
PCH_GPIO_UNUSED, /* 50: UNUSED */
PCH_GPIO_INPUT, /* 51: ALS_INT_L */
PCH_GPIO_INPUT, /* 52: SIM_DET */
PCH_GPIO_PIRQ, /* 53: TRACKPAD_INT_DX */
PCH_GPIO_PIRQ, /* 54: TOUCH_INT_L_DX */
PCH_GPIO_OUT_HIGH, /* 50: VP8_DISABLE_L */
PCH_GPIO_UNUSED, /* 51: UNUSED */
PCH_GPIO_UNUSED, /* 52: UNUSED */
PCH_GPIO_UNUSED, /* 53: UNUSED */
PCH_GPIO_UNUSED, /* 54: UNUSED */
PCH_GPIO_UNUSED, /* 55: UNUSED */
PCH_GPIO_UNUSED, /* 56: UNUSED */
PCH_GPIO_OUT_HIGH, /* 57: PP3300_CCD_EN */
PCH_GPIO_OUT_HIGH, /* 56: USB2_PWR_EN */
PCH_GPIO_OUT_HIGH, /* 57: USB3_PWR_EN */
PCH_GPIO_INPUT, /* 58: PCH_SPI_WP_D */
PCH_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */
PCH_GPIO_NATIVE, /* 60: NATIVE: SML0ALERT */
PCH_GPIO_OUT_HIGH, /* 59: PP3300_LAN_EN */
PCH_GPIO_NATIVE, /* 60: NATIVE: SMB0ALERT# */
PCH_GPIO_UNUSED, /* 61: UNUSED */
PCH_GPIO_UNUSED, /* 62: UNUSED */
PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */
@ -95,8 +95,8 @@ static const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_UNUSED, /* 69: UNUSED */
PCH_GPIO_UNUSED, /* 70: UNUSED */
PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */
PCH_GPIO_NATIVE, /* 72: NATIVE: PCH_BATLOW# */
PCH_GPIO_NATIVE, /* 73: NATIVE: SMB1ALERT# */
PCH_GPIO_UNUSED, /* 72: UNUSED */
PCH_GPIO_UNUSED, /* 73: UNUSED */
PCH_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */
PCH_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */
PCH_GPIO_UNUSED, /* 76: UNUSED */

104
src/mainboard/google/jecht/hda_verb.h
View file

@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -21,17 +21,7 @@ static const u32 mainboard_cim_verb_data[] = {
/* coreboot specific header */
0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283
0x10ec0283, // Subsystem ID
0x0000000d, // Number of jacks (NID entries)
0x0017ff00, // Function Reset
0x0017ff00, // Double Function Reset
0x000F0000, // Pad - get vendor id
0x000F0002, // Pad - get revision id
/* Bits 31:28 - Codec Address */
/* Bits 27:20 - NID */
/* Bits 19:8 - Verb ID */
/* Bits 7:0 - Payload */
0x0000000c, // Number of jacks (NID entries)
/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0283 */
0x00172083,
@ -41,64 +31,64 @@ static const u32 mainboard_cim_verb_data[] = {
/* Pin Widget Verb Table */
/* Pin Complex (NID 0x12) DMIC - Disabled */
0x01271cf0, //
0x01271d11, //
0x01271e11, //
0x01271f41, //
/* Pin Complex (NID 0x12) DMIC */
0x01271cf0,
0x01271d11,
0x01271e11,
0x01271f41,
/* Pin Complex (NID 0x14) SPKR-OUT - Internal Speakers */
0x01471c10, // group 1, cap 0
0x01471d01, // no connector, no jack detect
0x01471e17, // speaker out, analog
0x01471f90, // fixed function, internal, Location N/A
/* Pin Complex (NID 0x14) SPKR-OUT PORTD */
0x01471cf0,
0x01471d11,
0x01471e11,
0x01471f40,
/* Pin Complex (NID 0x17) MONO Out - Disabled */
0x01771cf0, //
0x01771d11, //
0x01771e11, //
0x01771f41, //
/* Pin Complex (NID 0x17) */
0x01771cf0,
0x01771d11,
0x01771e11,
0x01771f41,
/* Pin Complex (NID 0x18) Disabled */
0x01871cf0, //
0x01871d11, //
0x01871e11, //
0x01871f41, //
/* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */
0x01971c20, // group2, cap 0
/* Pin Complex (NID 0x18) MIC1 PORTB */
0x01971c11, // group 1, cap 1
0x01971d10, // black, jack detect
0x01971ea1, // Mic in, 3.5mm Jack
0x01971f03, // connector, External left panel
0x01971ea7, // mic in, analog
0x01971f03, // connector, left panel
/* Pin Complex (NID 0x1A) LINE1 - Internal Mic */
0x01a71c11, // group 1, cap 1
0x01a71d01, // no connector, no jack detect
0x01a71ea7, // mic in, analog connection
0x01a71f90, // Fixed function, internal, Location N/A
/* Pin Complex (NID 0x19) MIC2 PORTF */
0x01871cf0,
0x01871d11,
0x01871e11,
0x01871f41,
/* Pin Complex (NID 0x1B) LINE2 - Disabled */
0x01b71cf0, //
0x01b71d11, //
0x01b71e11, //
0x01b71f41, //
/* Pin Complex (NID 0x1A) LINE1 PORTC */
0x01a71cf0,
0x01a71d11,
0x01a71e11,
0x01a71f41,
/* Pin Complex (NID 0x1D) PCBeep */
/* Pin Complex (NID 0x1B) LINE2 PORTE */
0x01a71cf0,
0x01a71d11,
0x01a71e11,
0x01a71f41,
/* Pin Complex (NID 0x1d) PCBeep */
0x01d71c2d, // eapd low on ex-amp, laptop, custom enable
0x01d71d81, // mute spkr on hpout
0x01d71e15, // pcbeep en able, checksum
0x01d71f40, // no physical, Internal, Location N/A
0x01d71f40, // no physical, internal
/* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/
0x01e71cf0, //
0x01e71d11, //
0x01e71e11, //
0x01e71f41, //
/* Pin Complex (NID 0x1E) SPDIF-OUT */
0x01e71cf0,
0x01e71d11,
0x01e71e11,
0x01e71f41,
/* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack*/
0x02171c21, // group2, cap 1
/* Pin Complex (NID 0x21) HPOUT PORT-I */
0x02171c1f, // group1,
0x02171d10, // black, jack detect
0x02171e21, // HPOut, 3.5mm Jack
0x02171e21, // HPOut, 1/8 stereo
0x02171f03, // connector, left panel
/* Undocumented settings from Realtek (needed for beep_gen) */

178
src/mainboard/google/jecht/lan.c Normal file
View file

@ -0,0 +1,178 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <types.h>
#include <string.h>
#include <arch/io.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <vendorcode/google/chromeos/fmap.h>
#include "onboard.h"
static unsigned int search(char *p, char *a, unsigned int lengthp,
unsigned int lengtha)
{
int i, j;
/* Searching */
for (j = 0; j <= lengtha - lengthp; j++) {
for (i = 0; i < lengthp && p[i] == a[i + j]; i++) ;
if (i >= lengthp)
return j;
}
return lengtha;
}
static unsigned char get_hex_digit(char *offset)
{
unsigned char retval = 0;
retval = *offset - '0';
if (retval > 0x09) {
retval = *offset - 'A' + 0x0A;
if (retval > 0x0F)
retval = *offset - 'a' + 0x0a;
}
if (retval > 0x0F) {
printk(BIOS_DEBUG, "Error: Invalid Hex digit found: %c - 0x%02x\n",
*offset, (unsigned char)*offset);
retval = 0;
}
return retval;
}
static int get_mac_address(u32 *high_dword, u32 *low_dword,
u32 search_address, u32 search_length)
{
char key[] = "ethernet_mac";
unsigned int offset;
int i;
offset = search(key, (char *)search_address,
sizeof(key) - 1, search_length);
if (offset == search_length) {
printk(BIOS_DEBUG,
"Error: Could not locate '%s' in VPD\n", key);
return 0;
}
printk(BIOS_DEBUG, "Located '%s' in VPD\n", key);
offset += sizeof(key); /* move to next character */
*high_dword = 0;
/* Fetch the MAC address and put the octets in the correct order to
* be programmed.
*
* From RTL8105E_Series_EEPROM-Less_App_Note_1.1
* If the MAC address is 001122334455h:
* Write 33221100h to I/O register offset 0x00 via double word access
* Write 00005544h to I/O register offset 0x04 via double word access
*/
for (i = 0; i < 4; i++) {
*high_dword |= (get_hex_digit((char *)(search_address + offset))
<< (4 + (i * 8)));
*high_dword |= (get_hex_digit((char *)(search_address + offset + 1))
<< (i * 8));
offset += 3;
}
*low_dword = 0;
for (i = 0; i < 2; i++) {
*low_dword |= (get_hex_digit((char *)(search_address + offset))
<< (4 + (i * 8)));
*low_dword |= (get_hex_digit((char *)(search_address + offset + 1))
<< (i * 8));
offset += 3;
}
return *high_dword | *low_dword;
}
static void program_mac_address(u16 io_base, u32 search_address,
u32 search_length)
{
/* Default MAC Address of A0:00:BA:D0:0B:AD */
u32 high_dword = 0xD0BA00A0; /* high dword of mac address */
u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */
if (search_length != -1)
get_mac_address(&high_dword, &low_dword, search_address,
search_length);
if (io_base) {
printk(BIOS_DEBUG, "Realtek NIC io_base = 0x%04x\n", io_base);
printk(BIOS_DEBUG, "Programming MAC Address\n");
outb(0xc0, io_base + 0x50); /* Disable register protection */
outl(high_dword, io_base);
outl(low_dword, io_base + 0x04);
outb(0x60, io_base + 54);
outb(0x00, io_base + 0x50); /* Enable register protection again */
}
}
void lan_init(void)
{
char **vpd_region_ptr = NULL;
u32 search_length = find_fmap_entry("RO_VPD", (void **)vpd_region_ptr);
u32 search_address = (unsigned long)(*vpd_region_ptr);
u16 io_base = 0;
struct device *ethernet_dev = NULL;
/* Get NIC's IO base address */
ethernet_dev = dev_find_device(JECHT_NIC_VENDOR_ID,
JECHT_NIC_DEVICE_ID, 0);
if (ethernet_dev != NULL) {
io_base = pci_read_config16(ethernet_dev, 0x10) & 0xfffe;
/*
* Battery life time - LAN PCIe should enter ASPM L1 to save
* power when LAN connection is idle.
* enable CLKREQ: LAN pci config space 0x81h=01
*/
pci_write_config8(ethernet_dev, 0x81, 0x01);
}
if (io_base) {
/* Program MAC address based on VPD data */
program_mac_address(io_base, search_address, search_length);
/*
* Program NIC LEDS
*
* RTL8105E Series EEPROM-Less Application Note,
* Section 5.6 LED Mode Configuration
*
* Step1: Write C0h to I/O register 0x50 via byte access to
* disable 'register protection'
* Step2: Write xx001111b to I/O register 0x52 via byte access
* (bit7 is LEDS1 and bit6 is LEDS0)
* Step3: Write 0x00 to I/O register 0x50 via byte access to
* enable 'register protection'
*/
outb(0xc0, io_base + 0x50); /* Disable protection */
outb((JECHT_NIC_LED_MODE << 6) | 0x0f, io_base + 0x52);
outb(0x00, io_base + 0x50); /* Enable register protection */
}
}

71
src/mainboard/google/jecht/mainboard.c
View file

@ -35,9 +35,14 @@
#include <arch/interrupt.h>
#include <boot/coreboot_tables.h>
#include "hda_verb.h"
#include "ec.h"
#include "onboard.h"
void mainboard_suspend_resume(void)
{
/* Call SMM finalize() handlers before resume */
outb(0xcb, 0xb2);
}
#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN
static int int15_handler(void)
{
@ -47,20 +52,32 @@ static int int15_handler(void)
__func__, X86_AX, X86_BX, X86_CX, X86_DX);
switch (X86_AX) {
case 0x5f34:
/*
* Set Panel Fitting Hook:
* bit 2 = Graphics Stretching
* bit 1 = Text Stretching
* bit 0 = Centering (do not set with bit1 or bit2)
* 0 = video bios default
*/
X86_AX = 0x005f;
X86_CX = 0x0001;
res = 1;
break;
case 0x5f35:
/*
* Boot Display Device Hook:
* bit 0 = CRT
* bit 1 = RESERVED
* bit 2 = EFP
* bit 1 = TV (eDP) *
* bit 2 = EFP *
* bit 3 = LFP
* bit 4 = RESERVED
* bit 5 = EFP3
* bit 6 = EFP2
* bit 7 = RESERVED
* bit 4 = CRT2
* bit 5 = TV2 (eDP) *
* bit 6 = EFP2 *
* bit 7 = LFP2
*/
X86_AX = 0x005f;
X86_CX = 0x0008;
X86_CX = 0x0000;
res = 1;
break;
case 0x5f51:
@ -130,42 +147,7 @@ static void verb_setup(void)
static void mainboard_init(device_t dev)
{
mainboard_ec_init();
}
static int mainboard_smbios_data(device_t dev, int *handle,
unsigned long *current)
{
int len = 0;
len += smbios_write_type41(
current, handle,
BOARD_LIGHTSENSOR_NAME, /* name */
BOARD_LIGHTSENSOR_IRQ, /* instance */
BOARD_LIGHTSENSOR_I2C_BUS, /* segment */
BOARD_LIGHTSENSOR_I2C_ADDR, /* bus */
0, /* device */
0); /* function */
len += smbios_write_type41(
current, handle,
BOARD_TRACKPAD_NAME, /* name */
BOARD_TRACKPAD_IRQ, /* instance */
BOARD_TRACKPAD_I2C_BUS, /* segment */
BOARD_TRACKPAD_I2C_ADDR, /* bus */
0, /* device */
0); /* function */
len += smbios_write_type41(
current, handle,
BOARD_TOUCHSCREEN_NAME, /* name */
BOARD_TOUCHSCREEN_IRQ, /* instance */
BOARD_TOUCHSCREEN_I2C_BUS, /* segment */
BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */
0, /* device */
0); /* function */
return len;
lan_init();
}
// mainboard_enable is executed as first thing after
@ -174,7 +156,6 @@ static int mainboard_smbios_data(device_t dev, int *handle,
static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = mainboard_smbios_data;
#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN
/* Install custom int15 handler for VGA OPROM */
mainboard_interrupt_handlers(0x15, &int15_handler);

28
src/mainboard/google/jecht/onboard.h
View file

@ -20,21 +20,21 @@
#ifndef ONBOARD_H
#define ONBOARD_H
#define BOARD_LIGHTSENSOR_NAME "lightsensor"
#define BOARD_LIGHTSENSOR_IRQ 51 /* PIRQT */
#define BOARD_LIGHTSENSOR_I2C_BUS 2 /* I2C1 */
#define BOARD_LIGHTSENSOR_I2C_ADDR 0x44
#ifndef __ACPI__
void lan_init(void);
#endif
#define BOARD_TRACKPAD_NAME "trackpad"
#define BOARD_TRACKPAD_IRQ 37 /* PIRQV */
#define BOARD_TRACKPAD_WAKE_GPIO 12 /* GPIO12 */
#define BOARD_TRACKPAD_I2C_BUS 1 /* I2C0 */
#define BOARD_TRACKPAD_I2C_ADDR 0x67
/* defines for programming the MAC address */
#define JECHT_NIC_VENDOR_ID 0x10EC
#define JECHT_NIC_DEVICE_ID 0x8168
#define BOARD_TOUCHSCREEN_NAME "touchscreen"
#define BOARD_TOUCHSCREEN_IRQ 38 /* PIRQW */
#define BOARD_TOUCHSCREEN_WAKE_GPIO 25 /* GPIO25 */
#define BOARD_TOUCHSCREEN_I2C_BUS 2 /* I2C1 */
#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a
/* 0x00: White LINK LED and Amber ACTIVE LED */
#define JECHT_NIC_LED_MODE 0x00
/* NIC wake is GPIO 8 */
#define JECHT_NIC_WAKE_GPIO 8
/* WLAN wake is GPIO 10 */
#define JECHT_WLAN_WAKE_GPIO 10
#endif

52
src/mainboard/google/jecht/pei_data.c
View file

@ -25,43 +25,39 @@
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
pei_data->ec_present = 1;
pei_data->ec_present = 0;
/* One installed DIMM per channel -- can be changed by SPD init */
pei_data->dimm_channel0_disabled = 2;
pei_data->dimm_channel1_disabled = 2;
/* P0: LTE */
pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP,
/* P0: VP8 */
pei_data_usb2_port(pei_data, 0, 0x0064, 1, 0,
USB_PORT_MINI_PCIE);
/* P1: POrt A, CN10 */
/* P1: Port A, CN22 */
pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0,
USB_PORT_BACK_PANEL);
/* P2: CCD */
pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
USB_PORT_INTERNAL);
/* P3: BT */
/* P2: Port B, CN23 */
pei_data_usb2_port(pei_data, 2, 0x0040, 1, 1,
USB_PORT_INTERNAL);
/* P3: WLAN */
pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
USB_PORT_MINI_PCIE);
/* P4: Port B, CN6 */
/* P4: Port C, CN25 */
pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2,
USB_PORT_BACK_PANEL);
/* P5: EMPTY */
pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP,
USB_PORT_SKIP);
/* P6: SD Card */
pei_data_usb2_port(pei_data, 6, 0x0150, 1, USB_OC_PIN_SKIP,
USB_PORT_FLEX);
USB_PORT_INTERNAL);
/* P5: Port D, CN25 */
pei_data_usb2_port(pei_data, 5, 0x0040, 1, 2,
USB_PORT_INTERNAL);
/* P6: Card Reader */
pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP,
USB_PORT_INTERNAL);
/* P7: EMPTY */
pei_data_usb2_port(pei_data, 7, 0x0000, 0, USB_OC_PIN_SKIP,
pei_data_usb2_port(pei_data, 7, 0x0000, 0, 0,
USB_PORT_SKIP);
/* P1: Port A, CN6 */
/* P1: CN22 */
pei_data_usb3_port(pei_data, 0, 1, 0, 0);
/* P2: EMPTY */
pei_data_usb3_port(pei_data, 1, 0, USB_OC_PIN_SKIP, 0);
/* P3: EMPTY */
pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0);
/* P4: EMPTY */
pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0);
/* P2: CN23 */
pei_data_usb3_port(pei_data, 1, 1, 1, 0);
/* P3: CN25 */
pei_data_usb3_port(pei_data, 2, 1, 2, 0);
/* P4: CN25 */
pei_data_usb3_port(pei_data, 3, 1, 2, 0);
}

14
src/mainboard/google/jecht/romstage.c
View file

@ -28,6 +28,8 @@
#include <soc/romstage.h>
#include <mainboard/google/jecht/spd/spd.h>
#include "gpio.h"
#include "superio/ite/it8772f/it8772f.h"
#include "superio/ite/it8772f/early_serial.c"
void mainboard_romstage_entry(struct romstage_params *rp)
{
@ -35,9 +37,6 @@ void mainboard_romstage_entry(struct romstage_params *rp)
post_code(0x32);
/* Ensure the EC is in the right mode for recovery */
google_chromeec_early_init();
/* Initialize GPIOs */
init_gpios(mainboard_gpio_config);
@ -50,3 +49,12 @@ void mainboard_romstage_entry(struct romstage_params *rp)
/* Call into the real romstage main with this board's attributes. */
romstage_common(rp);
}
void mainboard_pre_console_init(void)
{
/* Early SuperIO setup */
it8772f_kill_watchdog();
it8772f_ac_resume_southbridge();
it8772f_enable_serial(PNP_DEV(IT8772F_BASE, IT8772F_SP1),
CONFIG_TTYS0_BASE);
}

79
src/mainboard/google/jecht/smihandler.c
View file

@ -30,12 +30,6 @@
#include <soc/nvs.h>
#include <soc/pm.h>
#include <soc/smm.h>
#include "ec.h"
/* Codec enable: GPIO45 */
#define GPIO_PP3300_CODEC_EN 45
/* WLAN / BT enable: GPIO46 */
#define GPIO_WLAN_DISABLE_L 46
int mainboard_io_trap_handler(int smif)
{
@ -54,43 +48,12 @@ int mainboard_io_trap_handler(int smif)
* For now, we force the return value to 0 and log all traps to
* see what's going on.
*/
//gnvs->smif = 0;
return 1;
}
static u8 mainboard_smi_ec(void)
{
u8 cmd = google_chromeec_get_event();
u32 pm1_cnt;
#if CONFIG_ELOG_GSMI
/* Log this event */
if (cmd)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
#endif
switch (cmd) {
case EC_HOST_EVENT_LID_CLOSED:
printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
/* Go to S5 */
pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
pm1_cnt |= (0xf << 10);
outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
break;
}
return cmd;
}
/* gpi_sts is GPIO 47:32 */
void mainboard_smi_gpi(u32 gpi_sts)
{
if (gpi_sts & (1 << (EC_SMI_GPI - 32))) {
/* Process all pending events */
while (mainboard_smi_ec() != 0)
;
}
}
void mainboard_smi_sleep(u8 slp_typ)
@ -98,60 +61,18 @@ void mainboard_smi_sleep(u8 slp_typ)
/* Disable USB charging if required */
switch (slp_typ) {
case 3:
if (smm_get_gnvs()->s3u0 == 0) {
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
google_chromeec_set_usb_charge_mode(
1, USB_CHARGE_MODE_DISABLED);
}
set_gpio(GPIO_PP3300_CODEC_EN, 0);
set_gpio(GPIO_WLAN_DISABLE_L, 0);
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
break;
case 5:
if (smm_get_gnvs()->s5u0 == 0) {
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
google_chromeec_set_usb_charge_mode(
1, USB_CHARGE_MODE_DISABLED);
}
set_gpio(GPIO_PP3300_CODEC_EN, 0);
set_gpio(GPIO_WLAN_DISABLE_L, 0);
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
break;
}
/* Disable SCI and SMI events */
google_chromeec_set_smi_mask(0);
google_chromeec_set_sci_mask(0);
/* Clear pending events that may trigger immediate wake */
while (google_chromeec_get_event() != 0)
;
}
int mainboard_smi_apmc(u8 apmc)
{
switch (apmc) {
case APM_CNT_ACPI_ENABLE:
google_chromeec_set_smi_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0)
;
google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
break;
case APM_CNT_ACPI_DISABLE:
google_chromeec_set_sci_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0)
;
google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
break;
}
return 0;

17
src/mainboard/google/jecht/spd/Elpida_EDJ4216EFBG.spd.hex
View file

@ -1,17 +0,0 @@
# Elpida EDJ4216EFBG-GN-F
92 12 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00
69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 81
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 02 FE 00 00 00 00 00 00 00 A1 CE
45 44 4A 34 32 31 36 45 46 42 47 2D 47 4E 2D 46
00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF

17
src/mainboard/google/jecht/spd/Hynix_HMT425S6AFR6A.spd.hex
View file

@ -1,17 +0,0 @@
# Hynix HMT425S6AFR6A-PBA
92 12 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00
69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 80 AD 01 00 00 00 00 00 00 FF AB
48 4D 54 34 32 35 53 36 41 46 52 36 41 2D 50 42
20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF

34
src/mainboard/google/jecht/spd/Makefile.inc
View file

@ -18,37 +18,3 @@
##
romstage-y += spd.c
SPD_BIN = $(obj)/spd.bin
# { GPIO47, GPIO9, GPIO13 }
SPD_SOURCES = Micron_4KTF25664HZ # 0b0000
SPD_SOURCES += Hynix_HMT425S6AFR6A # 0b0001
SPD_SOURCES += Elpida_EDJ4216EFBG # 0b0010
SPD_SOURCES += Micron_4KTF25664HZ # 0b0011
SPD_SOURCES += Micron_4KTF25664HZ # 0b0100
SPD_SOURCES += Hynix_HMT425S6AFR6A # 0b0101
SPD_SOURCES += Elpida_EDJ4216EFBG # 0b0110
SPD_SOURCES += empty # 0b0111
SPD_SOURCES += empty # 0b1000
SPD_SOURCES += empty # 0b1001
SPD_SOURCES += empty # 0b1010
SPD_SOURCES += empty # 0b1011
SPD_SOURCES += empty # 0b1100
SPD_SOURCES += empty # 0b1101
SPD_SOURCES += empty # 0b1110
SPD_SOURCES += empty # 0b1111
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
# Include spd rom data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
do echo -e -n "\\x$$c"; \
done; \
done > $@
cbfs-files-y += spd.bin
spd.bin-file := $(SPD_BIN)
spd.bin-type := 0xab

17
src/mainboard/google/jecht/spd/Micron_4KTF25664HZ.spd.hex
View file

@ -1,17 +0,0 @@
# Micron 4KTF25664HZ-1G6E1
92 11 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00
69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 80 2C 00 00 00 00 00 00 00 AD 75
34 4B 54 46 32 35 36 36 34 48 5A 2D 31 47 36 45
31 20 45 31 80 2C 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF

16
src/mainboard/google/jecht/spd/empty.spd.hex
View file

@ -1,16 +0,0 @@
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

118
src/mainboard/google/jecht/spd/spd.c
View file

@ -24,118 +24,18 @@
#include <soc/gpio.h>
#include <soc/pei_data.h>
#include <soc/romstage.h>
#include <ec/google/chromeec/ec.h>
#include <mainboard/google/jecht/ec.h>
#include <mainboard/google/jecht/gpio.h>
#include <mainboard/google/jecht/spd/spd.h>
static void mainboard_print_spd_info(uint8_t spd[])
{
const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 };
const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 };
const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };
const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
char spd_name[SPD_PART_LEN+1] = { 0 };
int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
int cols = spd_cols[spd[SPD_ADDRESSING] & 7];
int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];
int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
/* Module type */
printk(BIOS_INFO, "SPD: module type is ");
switch (spd[SPD_DRAM_TYPE]) {
case SPD_DRAM_DDR3:
printk(BIOS_INFO, "DDR3\n");
break;
case SPD_DRAM_LPDDR3:
printk(BIOS_INFO, "LPDDR3\n");
break;
default:
printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
break;
}
/* Module Part Number */
memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
spd_name[SPD_PART_LEN] = 0;
printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, "
, banks, ranks, rows, cols);
printk(BIOS_INFO, "density %d Mb\n", capmb);
printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
devw, busw);
if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
/* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
capmb / 8 * busw / devw * ranks);
}
}
/* Copy SPD data for on-board memory */
void mainboard_fill_spd_data(struct pei_data *pei_data)
{
int spd_bits[3] = {
SPD_GPIO_BIT0,
SPD_GPIO_BIT1,
SPD_GPIO_BIT2
};
int spd_gpio[3];
int spd_index;
int spd_file_len;
struct cbfs_file *spd_file;
spd_gpio[0] = get_gpio(SPD_GPIO_BIT0);
spd_gpio[1] = get_gpio(SPD_GPIO_BIT1);
spd_gpio[2] = get_gpio(SPD_GPIO_BIT2);
spd_index = spd_gpio[2] << 2 | spd_gpio[1] << 1 | spd_gpio[0];
printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d GPIO%d=%d)\n",
spd_index,
spd_bits[2], spd_gpio[2],
spd_bits[1], spd_gpio[1],
spd_bits[0], spd_gpio[0]);
spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin");
if (!spd_file)
die("SPD data not found.");
spd_file_len = ntohl(spd_file->len);
if (spd_index > 3)
pei_data->dimm_channel1_disabled = 3;
if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
spd_index = 0;
}
if (spd_file_len < SPD_LEN)
die("Missing SPD data.");
spd_index *= SPD_LEN;
memcpy(pei_data->spd_data[0][0],
((char *)CBFS_SUBHEADER(spd_file)) + spd_index, SPD_LEN);
/* Index 0-2 are 4GB config with both CH0 and CH1.
* Index 4-6 are 2GB config with CH0 only. */
if (spd_index > 3)
pei_data->dimm_channel1_disabled = 3;
else
memcpy(pei_data->spd_data[1][0],
((char *)CBFS_SUBHEADER(spd_file)) + spd_index, SPD_LEN);
/* Make sure a valid SPD was found */
if (pei_data->spd_data[0][0][0] == 0)
die("Invalid SPD data.");
mainboard_print_spd_info(pei_data->spd_data[0][0]);
pei_data->spd_addresses[0] = 0xa0;
pei_data->spd_addresses[1] = 0x00;
pei_data->spd_addresses[2] = 0xa4;
pei_data->spd_addresses[3] = 0x00;
pei_data->dimm_channel0_disabled = 2;
pei_data->dimm_channel1_disabled = 2;
// Enable 2x refresh mode
pei_data->ddr_refresh_2x = 1;
pei_data->dq_pins_interleaved = 1;
}

17
src/mainboard/google/jecht/spd/spd.h
View file

@ -20,23 +20,6 @@
#ifndef MAINBOARD_SPD_H
#define MAINBOARD_SPD_H
#define SPD_LEN 256
#define SPD_DRAM_TYPE 2
#define SPD_DRAM_DDR3 0x0b
#define SPD_DRAM_LPDDR3 0xf1
#define SPD_DENSITY_BANKS 4
#define SPD_ADDRESSING 5
#define SPD_ORGANIZATION 7
#define SPD_BUS_DEV_WIDTH 8
#define SPD_PART_OFF 128
#define SPD_PART_LEN 18
/* Jecht board memory configuration GPIOs */
#define SPD_GPIO_BIT0 13
#define SPD_GPIO_BIT1 9
#define SPD_GPIO_BIT2 47
struct pei_data;
void mainboard_fill_spd_data(struct pei_data *pei_data);