veyron*: sdram_get_ram_code() -> ram_code()
This enables RAM_CODE_SUPPORT for veyron* platforms and uses the generic gpio_get_binaries() function to read RAM_ID GPIOs. BUG=chrome-os-partner:31728 BRANCH=none TEST=built and booted on pinky Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ibc4c61687f1c59311cbf6b48371f9a9125dbe115 Reviewed-on: https://chromium-review.googlesource.com/227249 Reviewed-by: Julius Werner <jwerner@chromium.org>
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6 changed files with 30 additions and 46 deletions
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@ -27,6 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_SPI
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select EC_SOFTWARE_SYNC
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select RAM_CODE_SUPPORT
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select SOC_ROCKCHIP_RK3288
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select MAINBOARD_DO_NATIVE_VGA_INIT
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select MAINBOARD_HAS_BOOTBLOCK_INIT
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@ -35,3 +35,15 @@ uint8_t board_id(void)
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return id;
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}
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uint32_t ram_code(void)
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{
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uint32_t code;
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static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
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[1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
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code = gpio_base2_value(pins, ARRAY_SIZE(pins));
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printk(BIOS_SPEW, "RAM Config: %u.\n", code);
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return code;
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}
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@ -17,6 +17,7 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <boardid.h>
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#include <console/console.h>
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#include <gpio.h>
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#include <soc/sdram.h>
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@ -42,31 +43,9 @@ static struct rk3288_sdram_params sdram_configs[] = {
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 1111 */
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};
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#define GPIO_RAMCODE0 GPIO(8, A, 0)
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#define GPIO_RAMCODE1 GPIO(8, A, 1)
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#define GPIO_RAMCODE2 GPIO(8, A, 2)
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#define GPIO_RAMCODE3 GPIO(8, A, 3)
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u32 sdram_get_ram_code(void)
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{
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u32 code = 0;
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gpio_input(GPIO_RAMCODE0);
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gpio_input(GPIO_RAMCODE1);
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gpio_input(GPIO_RAMCODE2);
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gpio_input(GPIO_RAMCODE3);
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code = gpio_get(GPIO_RAMCODE3) << 3
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| gpio_get(GPIO_RAMCODE2) << 2
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| gpio_get(GPIO_RAMCODE1) << 1
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| gpio_get(GPIO_RAMCODE0) << 0;
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return code;
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}
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const struct rk3288_sdram_params *get_sdram_config()
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{
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u32 ramcode = sdram_get_ram_code();
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u32 ramcode = ram_code();
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if (ramcode >= ARRAY_SIZE(sdram_configs)
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|| sdram_configs[ramcode].dramtype == UNUSED)
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@ -27,6 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_SPI
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select EC_SOFTWARE_SYNC
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select RAM_CODE_SUPPORT
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select SOC_ROCKCHIP_RK3288
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select MAINBOARD_DO_NATIVE_VGA_INIT
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select MAINBOARD_HAS_BOOTBLOCK_INIT
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@ -35,3 +35,15 @@ uint8_t board_id(void)
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return id;
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}
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uint32_t ram_code(void)
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{
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uint32_t code;
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static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
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[1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
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code = gpio_base2_value(pins, ARRAY_SIZE(pins));
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printk(BIOS_SPEW, "RAM Config: %u.\n", code);
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return code;
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}
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@ -17,6 +17,7 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <boardid.h>
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#include <console/console.h>
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#include <gpio.h>
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#include <soc/sdram.h>
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@ -42,31 +43,9 @@ static struct rk3288_sdram_params sdram_configs[] = {
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 1111 */
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};
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#define GPIO_RAMCODE0 GPIO(8, A, 0)
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#define GPIO_RAMCODE1 GPIO(8, A, 1)
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#define GPIO_RAMCODE2 GPIO(8, A, 2)
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#define GPIO_RAMCODE3 GPIO(8, A, 3)
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u32 sdram_get_ram_code(void)
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{
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u32 code = 0;
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gpio_input(GPIO_RAMCODE0);
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gpio_input(GPIO_RAMCODE1);
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gpio_input(GPIO_RAMCODE2);
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gpio_input(GPIO_RAMCODE3);
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code = gpio_get(GPIO_RAMCODE3) << 3
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| gpio_get(GPIO_RAMCODE2) << 2
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| gpio_get(GPIO_RAMCODE1) << 1
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| gpio_get(GPIO_RAMCODE0) << 0;
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return code;
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}
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const struct rk3288_sdram_params *get_sdram_config()
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{
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u32 ramcode = sdram_get_ram_code();
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u32 ramcode = ram_code();
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if (ramcode >= ARRAY_SIZE(sdram_configs)
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|| sdram_configs[ramcode].dramtype == UNUSED)
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