cbtables: Add RAM config information

This adds the RAM config code to the coreboot tables. The purpose is
to expose this information to software running at higher levels, e.g.
to print the RAM config coreboot is using as part of factory tests.

The prototype for ram_code() is in boardid.h since they are closely
related and will likely have common code.

BUG=chrome-os-partner:31728
BRANCH=none
TEST=tested w/ follow-up CLs on pinky

Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Idd38ec5b6af16e87dfff2e3750c18fdaea604400
Reviewed-on: https://chromium-review.googlesource.com/227248
Reviewed-by: Julius Werner <jwerner@chromium.org>

src/Kconfig

@@ -1087,6 +1087,13 @@ config BOARD_ID_SUPPORT
 	  running on and reports it through the coreboot table to the rest of
 	  the system.
 
+config RAM_CODE_SUPPORT
+	bool "Discover RAM configuration code and store it in coreboot table"
+	default n
+	help
+	  If enabled, coreboot discovers RAM configuration (value obtained by
+	  reading board straps) and stores it in coreboot table.
+
 endmenu
 
 # These probably belong somewhere else, but they are needed somewhere.

src/include/boardid.h

@@ -23,5 +23,6 @@
 #include <stdint.h>
 
 uint8_t board_id(void);
+uint32_t ram_code(void);
 
 #endif /* __INCLUDE_BOARDID_H__ */

src/include/boot/coreboot_tables.h

@@ -270,6 +270,13 @@ struct lb_macs {
 	struct mac_address mac_addrs[0];
 };
 
+#define LB_TAG_RAM_CODE		0x0028
+struct lb_ram_code {
+	uint32_t tag;
+	uint32_t size;
+	uint32_t ram_code;
+};
+
 /* The following structures are for the cmos definitions table */
 #define LB_TAG_CMOS_OPTION_TABLE 200
 /* cmos header record */

src/lib/coreboot_table.c

@@ -251,6 +251,19 @@ static void lb_board_id(struct lb_header *header)
 #endif
 }
 
+static void lb_ram_code(struct lb_header *header)
+{
+#if CONFIG_RAM_CODE_SUPPORT
+	struct lb_ram_code *code;
+
+	code = (struct lb_ram_code *)lb_new_record(header);
+
+	code->tag = LB_TAG_RAM_CODE;
+	code->size = sizeof(*code);
+	code->ram_code = ram_code();
+#endif
+}
+
 static void lb_x86_rom_cache(struct lb_header *header)
 {
 #if CONFIG_ARCH_X86
@@ -592,6 +605,9 @@ unsigned long write_coreboot_table(
 	/* Add board ID if available */
 	lb_board_id(head);
 
+	/* Add RAM config if available */
+	lb_ram_code(head);
+
 	add_cbmem_pointers(head);
 
 	/* Add board-specific table entries, if any. */