After CB:86803, ${branch} variable is no longer valid. Use
${branch_name} instead ${branch} for generating the commit message.
TEST=./util/scripts/update_submodules -R 3rdparty/arm-trusted-firmware/
The script generates the new commit successfully.
Change-Id: Ia528379b8721e6d419984bab28de7cf427e42423
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87268
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To allow adding more scripts to the util/mtkheader folder, rename it to
util/mediatek. Also update description.md and regenerate
Documentation/util.md and util/README.md by util_readme.sh.
Change-Id: Ibc6ef9dddc541d2dd471898af431cadde231edca
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
As CB:71757 [1] updates Documentation/util.md and util/README.md
manually without modifying util/intelp2m/description.md, we port the
description changes back to that file.
[1] commit da54bd60af ("Documentation: Update information about
intelp2m")
Change-Id: I3d3f87517c445d650e9cea61448b28d005d46737
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87224
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
FMAP should not contain information about the memory map.
Done with the following command:
"find -name \*.fmd -exec sed -i 's/\(FLASH\).* \(.*\) /\1 \2 /' {} \;"
for AMD:
All addresses that amdfwtool expects as command line parameter have the
ADDR_REL_BIOS (flash address) address_mode setting. One exception is
the *_FW_A_POSITION and *_FW_B_POSITION addresses. But amdfwtool checks
if memory or flash addresses are passed and converts accordingly. So
changing the address from memory -> flash doesn't matter for the
resulting binary.
Since commit 41a162b7a8 ("soc/amd/phoenix/Makefile.inc: Pass APOB_NV
address as offset") and therefore since phoenix SOC, APOB_NV is passed
as flash offset. But before that the memory ABL always assumed a MMIO
address (no matter the address_mode) so we need to add a little quirk
for that.
tested: boot glinda based mainboard and also check that memory training
is still cached successfully in APOB_NV.
Change-Id: Iac86ef9be6b14817a65bf3a7ccb624d205ca3f99
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add the PLATFORM_FAEGAN element to the 'platform' enum and use it in the
code. The Faegan SoC is similar to the Glinda SoC, but has a different
PSP ID.
Change-Id: I40a3e9981696fc02a44fbf300d1b47060a4a398b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86940
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Other types of FWs in the BIOS table are defined by context. So the
BIOS binary should follow that.
TEST=Binary identical test on platforms before mendocino
Tested on Skyrim
Change-Id: I9c2f2983d03c913b28fbd87aa0925a32a4649d62
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85466
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It is more reasonable. And, in later change, the Level 1 should be
split with Level 2 and combined with EFS.
Change locate_bdt2_bios to locate_bdt_bios. This function is more
flexibile and covers both L1 and L2 BIOS directory table.
Change-Id: I74605013cf53a38686f4e1e5a89a4e6a870f1f4b
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84532
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is now drawn (indirectly) from main usb_port_config.
Also drop it from autoport.
Change-Id: I8c5e9b2016cf56538de06575181a0a6b738c6a28
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85925
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of guessing the default branch by iterating over a list of
branch names, use the branch that is configured as default by upstream.
Change-Id: I628b5a4e5228870c54719577e32dae169b0ceb2e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86803
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Newer recovery images change the manifest format yet again, so increase
the lookhead when parsing the bios_image field to ensure we can find it.
TEST=run `./crosfirmware.sh craaskbowl` without erroring out
Change-Id: Idb1862e38a82f3cec8db55993ccf421cf3572c6f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
The help text of cbfstool's memory map window assignment option
needs to be corrected to [--mmap flash-base:mmio-base:size] from
[--mmio flash-base:mmio-base:size].
P.S. The option --mmap was initially introduced by
commit 34a7e66faa ("util/cbfstool: Add a new mechanism to
provide a memory map").
Change-Id: I5f8224c8789e642fc68f6ae2242e8e7a7228c8de
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reduces the size of the Docker image by removing all unnecessary files.
Change-Id: Ib8c658799217c3b6595e3b5fce8f5c8238054c45
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Instead of a pointer to a function for analyzing the pad name, provide
GPP group slice with pad names to the parser. This will get rid of some
functions and files and make the code cleaner.
TEST:
- 'make test' = PASS;
- 'intelp2m -file parser/testlog/inteltool_test.log' = no errors.
Change-Id: I0d7818d3892450a37bffbf1ffd9524888e4675bf
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
According to the architecture, this is part of the common block.
TEST: 'make test' = PASS
Change-Id: I6390182ab00d9ebd787e8da6f341e3ef85572991
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71235
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- embed the base platform and redefine its methods if they differ;
- separate the macro structures from the platform;
- move more functions to common;
- undo use of a single global instance of the microstructure.
TEST:
1) 'make test' = PASS
2) './intelp2m -p cnl -iiii -file inteltool.log' = gpio.h before and
after the commit is the same.
Change-Id: I2e0aa56efa2430ac6524c6977f8b6fd13113edf9
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71167
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Split the parser code into several packages to make its testing of its
functions more convenient and detailed. This also makes embedding the
parser in third-party applications more flexible - there is no need to
use all the functionality of the parser.
- Clean up code and remove unnecessary objects to make intelp2m simpler
and more readable.
- Change the common macro format to be consistent with the new parser.
- Rename the results directory containing gpio.h to output to avoid
confusion with the generator package directory.
- At the moment there is no mechanism for setting the Ownership flag.
This will be added in later versions.
Tests:
- make test = PASS
- gpio.h for Apollo Lake before and after the patch is the same
Change-Id: I9a29322dd31faf9ae100165f08f207360cbf9f80
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
The utility can parse the value of non-DWx registers, if they are
present in the inteltool dump. However, the functions that allow the
inteltool utility to print the value of such registers have not been
added to the master branch, and it makes no sense to support such
functions in intelp2m, besides, their implementation is far from ideal.
Remove this unused functionality. This will be restored in the future in
a different form and after corresponding changes in inteltool.
TEST: make test = PASS
Change-Id: If5c77ff942a620897c085be4135cb879a0d40a00
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56887
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add logging to a file, ./logs.txt by default. --logs option is used to
override this path. Error messages are duplicated to the console.
Change-Id: I97aba146b6d8866a7fa46bac80c27c0896b26cf7
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70542
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Split all methods between DW0 and DW1 to avoid the mistake of using any
DW0 method with DW1 receiver and make the code safer. Also make some
code style fixes.
TEST: make test = PASS
Change-Id: Id64e2a5e29f1d561597004ac83d32e3c80c16ebd
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70309
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Reduce the number of methods for updating settings and redefine types
to make the code cleaner and more readable.
- Move the configuration to the p2m package to add settings from new
utilities based on the intelp2m code.
- Make some code style fixes.
TEST: make test = PASS
Change-Id: Ia1b19ae3122bcf6ec740ae4683d62f31570670b1
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Exclude the template to parse gpio.h, since coreboot no longer has such
files with raw DW register values. The new GPIO config should be
generated using inteltool.log only.
TEST: make test = PASS
Change-Id: I07124cca487f11641c4e107134efb8cfc29c6731
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70307
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
For adding missing \n, find all potential missings by below script
and apply manual checks and fixes.
grep -nE "(DEBUG|ERROR)\(\".+[^\\n]\"" util/cbfstool/ -r
For using __func__ in debug message, below script is used with
manual checks and fixes.
grep -nE "DEBUG\(.+:" util/cbfstool/ -r
Change-Id: I3e2c225dc16a65470f9f94db89d8ec3711e781c8
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86567
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace all occurrences of u8, u16, u32 and u64 with their respective
alternatives of uint8_t. There is no need to unnecessarily compress code
by using standard types aliases.
BUG=b:391874512
TEST=Compile cbmem
Change-Id: I4fdb4a31923368342ef218144f8cb44624cd4b2a
Signed-off-by: Jakub Czapiga <czapiga@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
We need to know how many combo entries have been processed.
It will be checked in functions in later change.
Change-Id: I4b026b0630a18d1f46bff98ffe5f11e7f930d7a8
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85590
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clean up the code to make it more logical.
This is for later changes to reorder the PSP Level 1, Level 2, ISH and
BIOS tables.
TEST=Identical test on all AMD platform
Change-Id: I5f7213fd42c7f0ff5ecd9e504a6654cdfb1e3513
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84531
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For A/B recovery, it is better, even though it is not mandatory, to
put BIOS level 2 table next to its PSP level2. So the relative
addresses of BIOS table are the same. So all the data in B could be a
copy of A.
Identical binary test on all non A/B recovery platform.
Booting test on Majolica with A/B recovery enabled.
Change-Id: Ia25277d307329a2fa66d38d1a7fc21b18246cfe6
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Add the tooling necessary to build an Image that can be found and
started by ROM code of the JH7110 SOC.
source: https://github.com/starfive-tech/Tools
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Iab16c1e1f15f24e85c0ef1a3e838d024e1e49286
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83849
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Local tags (e.g. to keep track of builds) should not be used to describe
a board status report. This has happened in some cases, e.g. [1].
According to the Git 2.41.0 manual for git-describe, the '--tagged'
parameter is a way to also use any "lightweight (non-annotated) tag" in
addition to annotated tags, which are always used even without this
parameter. All coreboot release tags seem to be annotated, so this
option should be safe to drop.
[1] https://review.coreboot.org/plugins/gitiles/board-status/+/b8c47429bad5afc5cd7f798cad3dece9790a1f83
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Change-Id: I54b302415e569a3385559cc85323ce34462042ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79837
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The address field of each PSP or BIOS entry defines the location of
the entry.
For the family newer than Cezanne, the upper 2 bits define the address
mode. In table header, the address mode of the table is set. They have
the same definition.
Address Mode 0: Physical Address
Address Mode 1: Relative Address to entire BIOS image
Address Mode 2: Relative Address to PSP/BIOS directory
Address Mode 3: Relative Address to slot N
In common case, the address mode of entry should be the same as its
table. In spec, it says, "attribute is ignored if the directory
address mode is not 2 or 3",
In the old code, if the header defines address mode as relative BIOS(1),
the entry address mode is not set. That meets the spec. PSP doesn't
use, but amdfwtool can use it to record the address mode and transfer
it to table. That can reduce the code complexity.
Identidal binary test passes on platforms which are not based on
Cezanne, V2000A, Genoa. Booting test passes on Majolica/Cezanne.
Change-Id: I156b315d350d9e7217afc7442ca80277bb7f9095
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84530
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This commit adds a new event type, `ELOG_TYPE_LOW_BATTERY_INDICATOR`,
to the event log. This event is logged when the system boots due to
a low battery condition. It includes the reason for the shutdown,
currently only supporting "Power Off".
BUG=b:339673254
TEST=Able to capture the eventlog for low battery boot event.
```
> elogtool list
9 | 2025-02-03 09:44:19+0530 | Low Battery Boot | Power Off
```
Change-Id: I5cc5e5f540657c7dfd174a4928e697a272da813a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
PcieRpLtrEnable[] is a boolean, so use true false.
Change-Id: I4b557683b7897487dedfef0bf77e60b0dab9cbcf
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86193
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PcieRpEnable[] is a boolean, so use true false instead of 0 1.
Change-Id: I8e67a33f82b7dfa1864016ccd5cd1b7ec119c528
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
All of the other targets support invoking the build with the full target
arch name. RISC does not. Update the script to allow riscv64-elf to
invoke the build the same way that riscv-elf does to minimize name
mangling and exceptions needed for tooling surrounding the
architecture name in paths. Leave riscv-elf in tact as an option so
we don't break anyone else.
BUG=None
TEST=./util/crossgcc/buildgcc --platform riscv64-elf
Change-Id: Ie737855053e00205ca85f54436c224ab3a1283d9
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Add the printing of the missing libstdcxx path in the warning string
when the path check fails. Also resolve the use of the variable in
the conditional statement by surrounding it with quotes.
BUG=None
TEST=Build with invalid libstdcxx path
Change-Id: I195718e43ea842970f5fa986315c9e9f11395362
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86148
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some newer boards (like google/skyrim) use a separate line for each
field, so adjust parsing to accommodate that.
TEST=run `bash crosfirmware.sh` for frostflow, grunt, careena.
Change-Id: I3af38d3577f1390c999ad5e6df0fa2c4c4382245
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Also add an interface for printing macros to override this in the test
and not create a new gpio file for comparison.
Change-Id: I16c9b4451cd4418b49043a925cb879a982a56461
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67701
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the aliases are used and already contain the device name,
there's reason to generate these in the first place.
TEST=Ran autoport with logs from ASRock Z77 Extreme4.
Change-Id: I3378801f5a997a802da61f2b7c4e820f39064019
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85822
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since add-int is intended for manipulating options stored as integers in
CBFS (such as SeaBIOS runtime config options), removing the file so that
it can be re-added with a new value is a common action. Attempt to
remove the existing integer automatically if it already exists to remove
the need for the extra step.
Change-Id: I5a0ac409fc9b91a4f7c0c35650875d6211ac2b25
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86009
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
